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The following terms and abbreviations are used in the document.

•

Interrupt vector base register (IVBR)

•

One spurious interrupt vector (at address vector base

1

 + 0x0010).

•

One non-maskable system call interrupt vector request (at address vector base + 0x0012).

•

Three non-maskable access violation interrupt vector requests (at address vector base + 0x0014

−

0x0018).

•

2–109 I bit maskable interrupt vector requests (at addresses vector base + 0x001A–0x00F2).

•

Each I bit maskable interrupt request has a configurable priority level and can be configured to be
handled by either the CPU or the XGATE module

2

.

•

I bit maskable interrupts can be nested, depending on their priority levels.

•

One X bit maskable interrupt vector request (at address vector base + 0x00F4).

•

One non-maskable software interrupt request (SWI) or background debug mode vector request (at
address vector base + 0x00F6).

•

One non-maskable unimplemented op-code trap (TRAP) vector (at address vector base + 0x00F8).

•

Three system reset vectors (at addresses 0xFFFA–0xFFFE).

•

Determines the highest priority XGATE and interrupt vector requests, drives the vector to the
XGATE module or to the bus on CPU request, respectively.

•

Wakes up the system from stop or wait mode when an appropriate interrupt request occurs or
whenever XIRQ is asserted, even if X interrupt is masked.

•

XGATE can wake up and execute code, even with the CPU remaining in stop or wait mode.

CCR

Condition Code Register (in the S12X CPU)

DMA

Direct Memory Access

INT

Interrupt

IPL

Interrupt Processing Level

ISR

Interrupt Service Routine

MCU

Micro-Controller Unit

XGATE

refers to the XGATE co-processor; XGATE is an optional feature

IRQ

refers to the interrupt request associated with the IRQ pin

XIRQ

refers to the interrupt request associated with the XIRQ pin

1. The vector base is a 16-bit address which is accumulated from the contents of the interrupt vector base register (IVBR, used

as upper byte) and 0x00 (used as lower byte).

2. The IRQ interrupt can only be handled by the CPU