Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256

Модели

DEMO9S12XHY256

Interrupt (S12XINTV2)

MC9S12XHY-Family Reference Manual, Rev. 1.04

184

Freescale Semiconductor

4.1.4

Block Diagram

Figure 4-1

shows a block diagram of the XINT module.

Figure 4-1. XINT Block Diagram

4.2

External Signal Description

The XINT module has no external signals.

Wake Up

Current

RQST

IVBR

One Set Per Channel

XGATE
Interrupts

XGATE
Requests

Interrupt
Requests

Interrupt Requests

CPU

Vector

Address

New
IPL

IPL

(Up to 108 Channels)

RQST

XGATE Request Route,

PRIOLVLn

Priority Level

= bits from the channel configuration

in the associated configuration register

INT_XGPRIO

= XGATE Interrupt Priority

IVBR

= Interrupt Vector Base

IPL

= Interrupt Processing Level

PRIOLVL0

PRIOLVL1

PRIOLVL2

INT_XGPRIO

Peripheral

Vector
ID

To XGATE Module

Priority

Decoder

CPU

ior

ity

Decoder

Non I Bit Maskable

Channels

Wake up

XGATE

IRQ Channel