Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256

Модели

DEMO9S12XHY256

Device Overview MC9S12XHY-Family

MC9S12XHY-Family Reference Manual, Rev. 1.04

Freescale Semiconductor

1.8

System Clock Description

For the LCD CLK in

, it is always connected to the CRG LCD

clok output, which is from OSC clock, see

generator module (CRG) provides the internal clock signals for the core and all peripheral modules.

shows the clock connections from the CRG to all modules.

Consult the S12XECRG section for details on clock generation.

NOTE

The XHY and XS family uses the XE family clock and reset generator
module. Therefore all CRG references are related to S12XECRG.

Figure 1-5. Clock Connections

The system clock can be supplied in several ways enabling a range of system operating frequencies to be
supported:

•

The on-chip phase locked loop (PLL)

SCI0 . . SCI 1

SPI0

ATD0

CAN0..CAN1

CRG

Bus Clock

EXTAL

XTAL

Core Clock

Oscillator Clock

RAM

S12X

FLASH

TIM

PIM

LCD

IIC

PWM

SSD

Lcd Clock