Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256

Freescale Semiconductor

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When a reset occurs, MCU registers and control bits are initialized. Refer to the respective block sections
for register reset states.

On each reset, the Flash module executes a reset sequence to load Flash configuration registers.

On each reset, the Flash module will hold CPU activity while loading Flash module registers from the
Flash memory. If double faults are detected in the reset phase, Flash module protection and security may
be active on leaving reset. This is explained in more detail in the Flash module section.

If a reset occurs while any Flash command is in progress, that command will be immediately aborted. The
state of the word being programmed or the sector/block being erased is not guaranteed.

Refer to the PIM section for reset configurations of all peripheral module ports.

The RAM arrays are not initialized out of reset.

Vector base + $3C

to

Vector base + $14

Reserved

Vector base + $12

System Call Interrupt (SYS)

—

None

-

-

Vector base + $10

Spurious interrupt

—

None

-

-

1. 16 bits vector address based

9S12HY64 family LVI/API/HTI vector number is $8A-$86, while
9S12XHY256 is $80-$7C;9S12HY64 family ATD Compare interrupt
number is $84, while 9S12HY64 family is $3E;9S12HY64 family has
no SYS vector; 9S12HY64 family Spurious interrupt vector number
is $80.