Справочник Пользователя для Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256

Freescale Semiconductor

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Consult the ATD section for information about the analog-to-digital converter module. References to
freeze mode are equivalent to active BDM mode.

Further to the 12 externally available channels, ATD0 features an extra channel[17] that is connected to
the internal temperature sensor at device level. To access this channel ATD must use the channel encoding
SC:CD:CC:CB:CA = 1:0:0:0:1 in ATDCTL5. For more temperature sensor information, please refer to

The device must be configured with the internal voltage regulator enabled. Operation in conjunction with
an external voltage regulator is not supported.

The API trimming register APITR is loaded from the Flash IFR option field at global address 0x40_00F0
bits[5:0] during the reset sequence. Currently factory programming of this IFR range is not supported.

Read access to reserved VREG register space returns “0”. Write accesses have no effect. This device does
not support access abort of reserved VREG register space.

The VREG high temperature trimming register bits VREGHTTR[3:0] are loaded from the internal Flash
during the reset sequence. To use the high temperature interrupt within the specified limits (T

HTIA

and

T

HTID

) these bits must be loaded with 0x8. Currently factory programming is not supported.

The device temperature can be monitored on ATD0 channel[17]. The internal bandgap reference voltage
can also be mapped to ATD0 analog input channel[17]. The voltage regulator VSEL bit when set, maps
the bandgap and, when clear, maps the temperature sensor to ATD0 channel[17].

The XCLKS is an input signal which controls whether a crystal in combination with the internal loop
controlled (low power) Pierce oscillator is used or whether full swing Pierce oscillator/external clock
circuitry is used.

The XCLKS signal selects the oscillator configuration during reset low phase while a clock quality check
is ongoing. This is the case for:

•

 Power on reset or low-voltage reset

•

 Clock monitor reset

•

 Any reset while in self-clock mode or full stop mode

The selected oscillator configuration is frozen with the rising edge of the RESET pin in any of these above
described reset cases.