Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
228
Freescale Semiconductor
2.4.3.34
Port P Data Register (PTP)
Table 2-59. API_EXTCLK Routing Options
APICLKS7
API_EXTCLK Associated Pin
0
PB1 (100 LQFP)
PP0 (64/48/32 LQFP)
N.C. (20TSSOP)
PP0 (64/48/32 LQFP)
N.C. (20TSSOP)
1
PS7
Table 2-60. Package Options
PKGCR2
PKGCR1
PKGCR0
Selected Package
1
1
1
Reserved
1
1
Reading this value indicates an illegal code write or uninitialized factory programming.
1
1
0
100 LQFP
1
0
1
Reserved
1
0
0
64 LQFP
0
1
1
48 LQFP
0
1
0
Reserved
0
0
1
32 LQFP
0
0
0
20 TSSOP
Address 0x0258 (
,
)
Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
PTP7
PTP6
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
W
Reset
0
0
0
0
0
0
0
0
Address 0x0258 (
)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
PTP5
PTP4
PTP3
PTP2
PTP1
PTP0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-35. Port P Data Register (PTP)