Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
230
Freescale Semiconductor
2.4.3.36
Port P Data Direction Register (DDRP)
2.4.3.37
Port P Pull Device Enable Register (PERP)
Address 0x025A (
)
Access: User read/write
1
1
Read: Anytime
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
DDRP7
DDRP6
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
W
Reset
0
0
0
0
0
0
0
0
Address 0x025A (
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
DDRP5
DDRP4
DDRP3
DDRP2
DDRP1
DDRP0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-37. Port P Data Direction Register (DDRP)
Table 2-63. DDRP Register Field Descriptions
Field
Description
7-0
DDRP
Port P data direction—
This bit determines whether the associated pin is an input or output.
This bit determines whether the associated pin is an input or output.
1 Associated pin configured as output
0 Associated pin configured as input
0 Associated pin configured as input
Address 0x025C (
Access: User read/write
1
1
Read: Anytime
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
PERP7
PERP6
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
W
Reset
0
0
0
0
0
0
0
0
Address 0x025C (
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
PERP5
PERP4
PERP3
PERP2
PERP1
PERP0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-38. Port P Pull Device Enable Register (PERP)