Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
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Модели
TWR-S12GN32-KIT
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
234
Freescale Semiconductor
2.4.3.41
Reserved Registers
NOTE
Addresses 0x0260-0x0261 are reserved for ACMP registers in
and
only. Refer to ACMP section “ACMP Control Register (ACMPC)” and
“ACMP Status Register (ACMPS)”.
“ACMP Status Register (ACMPS)”.
2.4.3.42
Port J Data Register (PTJ)
Address 0x0268 (
,
)
Access: User read/write
1
1
Read: Anytime. The data source is depending on the data direction value.
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
W
Reset
0
0
0
0
0
0
0
0
Address 0x0268 (
)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
PTJ3
PTJ2
PTJ1
PTJ0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-42. Port J Data Register (PTJ)
Table 2-68. PTJ Register Field Descriptions
Field
Description
7-0
PTJ
Port J general-purpose input/output data—Data Register
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.
When not used with an alternative signal, the associated pin can be used as general-purpose I/O. In
general-purpose output mode the port data register bit value is driven to the pin.
If the associated data direction bit is set to 1, a read returns the value of the port data register bit, otherwise the
buffered pin input state is read.