Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Port Integration Module (S12GPIMV1)
MC9S12G Family Reference Manual,
Rev.1.23
232
Freescale Semiconductor
2.4.3.39
Port P Interrupt Enable Register (PIEP)
Read: Anytime
2.4.3.40
Port P Interrupt Flag Register (PIFP)
Address 0x025E (
)
Access: User read/write
1
1
Read: Anytime
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
PIEP7
PIEP6
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
W
Reset
0
0
0
0
0
0
0
0
Address 0x025E (
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
PIEP5
PIEP4
PIEP3
PIEP2
PIEP1
PIEP0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-40. Port P Interrupt Enable Register (PIEP)
Table 2-66. PIEP Register Field Descriptions
Field
Description
7-0
PIEP
Port P interrupt enable—
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
0 Interrupt is disabled (interrupt flag masked)
Address 0x025F (
Access: User read/write
1
7
6
5
4
3
2
1
0
R
PIFP7
PIFP6
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
W
Reset
0
0
0
0
0
0
0
0
Address 0x025F (
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
PIFP5
PIFP4
PIFP3
PIFP2
PIFP1
PIFP0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-41. Port P Interrupt Flag Register (PIFP)