Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
![Freescale Semiconductor](https://files.manualsbrain.com/attachments/3bb6ed54ced79535c16e15272d951c615eff7542/common/fit/150/50/1f2ce9b696676e671c4a5e26a6d7f7adf81e5b28c3d837b6200a14eeaf20/brand_logo.gif)
Модели
TWR-S12GN32-KIT
Serial Peripheral Interface (S12SPIV5)
MC9S12G Family Reference Manual,
Rev.1.23
714
Freescale Semiconductor
21.3.2.4
SPI Status Register (SPISR)
Read: Anytime
Write: Has no effect
1
1
0
0
0
1
28
892.86 kbit/s
1
1
0
0
1
0
56
446.43 kbit/s
1
1
0
0
1
1
112
223.21 kbit/s
1
1
0
1
0
0
224
111.61 kbit/s
1
1
0
1
0
1
448
55.80 kbit/s
1
1
0
1
1
0
896
27.90 kbit/s
1
1
0
1
1
1
1792
13.95 kbit/s
1
1
1
0
0
0
16
1.5625 Mbit/s
1
1
1
0
0
1
32
781.25 kbit/s
1
1
1
0
1
0
64
390.63 kbit/s
1
1
1
0
1
1
128
195.31 kbit/s
1
1
1
1
0
0
256
97.66 kbit/s
1
1
1
1
0
1
512
48.83 kbit/s
1
1
1
1
1
0
1024
24.41 kbit/s
1
1
1
1
1
1
2048
12.21 kbit/s
Module Base +0x0003
7
6
5
4
3
2
1
0
R
SPIF
0
SPTEF
MODF
0
0
0
0
W
Reset
0
0
1
0
0
0
0
0
= Unimplemented or Reserved
Figure 21-6. SPI Status Register (SPISR)
Table 21-7. SPISR Field Descriptions
Field
Description
7
SPIF
SPIF Interrupt Flag — This bit is set after received data has been transferred into the SPI data register. For
information about clearing SPIF Flag, please refer to
information about clearing SPIF Flag, please refer to
0 Transfer not yet complete.
1 New data copied to SPIDR.
1 New data copied to SPIDR.
Table 21-6. Example SPI Baud Rate Selection (25 MHz Bus Clock)
SPPR2
SPPR1
SPPR0
SPR2
SPR1
SPR0
Baud Rate
Divisor
Baud Rate