Техническая Спецификация для Freescale Semiconductor Tower System Eval Kit for MC9S12GN32 TWR-S12GN32-KIT TWR-S12GN32-KIT
Модели
TWR-S12GN32-KIT
Serial Peripheral Interface (S12SPIV5)
MC9S12G Family Reference Manual,
Rev.1.23
716
Freescale Semiconductor
21.3.2.5
SPI Data Register (SPIDR = SPIDRH:SPIDRL)
Read: Anytime; read data only valid when SPIF is set
Write: Anytime
The SPI data register is both the input and output register for SPI data. A write to this register
allows data to be queued and transmitted. For an SPI configured as a master, queued data is
transmitted immediately after the previous transmission has completed. The SPI transmitter empty
flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data.
allows data to be queued and transmitted. For an SPI configured as a master, queued data is
transmitted immediately after the previous transmission has completed. The SPI transmitter empty
flag SPTEF in the SPISR register indicates when the SPI data register is ready to accept new data.
Received data in the SPIDR is valid when SPIF is set.
If SPIF is cleared and data has been received, the received data is transferred from the receive shift
register to the SPIDR and SPIF is set.
register to the SPIDR and SPIF is set.
If SPIF is set and not serviced, and a second data value has been received, the second received data
is kept as valid data in the receive shift register until the start of another transmission. The data in
the SPIDR does not change.
is kept as valid data in the receive shift register until the start of another transmission. The data in
the SPIDR does not change.
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced before the start of
a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF
remains set (see
a third transmission, the data in the receive shift register is transferred into the SPIDR and SPIF
remains set (see
If SPIF is set and valid data is in the receive shift register, and SPIF is serviced after the start of a
third transmission, the data in the receive shift register has become invalid and is not transferred
into the SPIDR (see
third transmission, the data in the receive shift register has become invalid and is not transferred
into the SPIDR (see
3
SPIDRH can be written repeatedly without any effect on SPTEF. SPTEF Flag is cleared only by
writing to SPIDRL after reading SPISR with SPTEF == 1.
writing to SPIDRL after reading SPISR with SPTEF == 1.
Module Base +0x0004
7
6
5
4
3
2
1
0
R
R15
R14
R13
R12
R11
R10
R9
R8
W
T15
T14
T13
T12
T11
T10
T9
T8
Reset
0
0
0
0
0
0
0
0
Figure 21-7. SPI Data Register High (SPIDRH)
Module Base +0x0005
7
6
5
4
3
2
1
0
R
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
Reset
0
0
0
0
0
0
0
0
Figure 21-8. SPI Data Register Low (SPIDRL)