Техническая Спецификация для Analog Devices AD5560 Evaluation Board EVAL-AD5560EBUZ EVAL-AD5560EBUZ

Модели

EVAL-AD5560EBUZ

Data Sheet

AD5560

Rev. D | Page 37 of 68

POLES AND ZEROS IN A TYPICAL SYSTEM

Typical closed loop systems have one dominant pole in the
feedback path, providing −20 dB/decade gain roll off and 90°
of phase shift so that the gain decreases to 0 dB where there
is a conservative 90° of phase margin.
The AD5560 has compensation options to help cope with the
various load conditions that a DPS is presented with.

MINIMIZING THE NUMBER OF EXTERNAL

COMPENSATION COMPONENTS

Note that, depending on the range of load conditions, not all
external capacitors are required.

Pins

There are five external C

pins. All five pins are used

in the autocompensation mode to choose a suitable capacitor,
depending on the load being driven. To reduce component
count, it is possible to connect just one capacitor, for instance,
C

to the C

, C

, and C

pins. Therefore, when any of the

smallest three external capacitors are selected, the same physical
capacitor is used because it is connected to all three pins. A
disadvantage here is that the larger C

capacitor should be

bigger than optimal and may increase settling time of the
whole circuit (particularly the measure current).

Pins

To make the AD5560 stable with any unknown capacitor
from 0 pF to 160 μF, all four C

capacitors are required.

However, if the range of load is from 0 pF to 20 µF, then
C

can be omitted. Similarly, if the load range is from 0 pF to

2.2 µF, then C

and C

can be omitted. Only C

is required

in autocompensation mode.
Note that safe mode, which makes the device stable in any
load from 0 pF to 160 μF, simply switches in all of the four
C

capacitors. Stability into 160 μF is assured only if all four

capacitors are present; otherwise, the maximum capacitor for
stability is reduced to 20 μF, 2.2 μF, or 220 nF, depending on
how many capacitors are missing.

EXTRA POLES AND ZEROS IN THE AD5560

The Effect of C

is switched on at all times. C

, C

, and C

can be con-

nected in addition to C

to slow down the force amplifier loop.

In the ±500 mA range looking into a small load capacitor, with
only C

connected, the ac gain vs. phase response results in

~90° of phase margin and a unity gain bandwidth (UGB) of
~400 kHz.

The Effect of C

The output of the AD5560 passes through a sense resistor to
the DUT. Coupled with the load capacitor, this sense resistor
can act as a low-pass filter that adds phase shift and decreases
phase margin (particularly in the low current ranges where the
sense resistors are large).

Placing a capacitor in parallel with this sense resistor provides
an ac feedforward path to the DUT. Therefore, at high frequen-
cies, the DUT is driven through the C

capacitor rather than

through the sense resistor.
Note that each C

output has an output impedance of about

3 Ω. This is very small compared to the sense resistors of the
low current ranges but not so for the highest current ranges.
Therefore, the C

capacitors are most effective in the low current

ranges but are of lesser benefit in higher current ranges.
As shown in the force amplifier diagram (see Figure 57), there
is a pole at 1/( R

SENSE

× [C

+ C

]) and a zero at 1/[ R

SENSE

× C

Therefore, the output impedance of each C

output, at around

1 Ω, limits the improvement available by using the C

capaci-

tors. For a large load capacitance, there is still a pole at −1/[1 Ω
× C

] above which the phase improvement is lost. If there is

also a cable resistance to the DUT, or if C

has significant ESR,

this should be added to the 1 Ω to calculate the pole frequency.
If C

is chosen to be bigger than the load capacitance, it can

dominate the settling time and slow down the settling of the
whole circuit. Also, it directly affects the time taken to measure
a current (R

SENSE

× C

The Effect of R

When the load capacitance is known, R

can be used to optim-

ize the response of the AD5560. Because the C

buffers have

some output impedance of about 1 Ω, there is likely to be some
additional resistance to the DUT. There can still be an output
pole associated with this resistance and the load capacitance,
C

, 1/[R

× C

] (where R

= the series/parallel combination of

the sense resistor, the C

output impedance, the C

capacitor

ESR, and the cable to DUT). This is particularly significant for
larger load capacitances in any current range. By programming
a zero into the loop response by setting R

(in series with C

it is possible to cancel this pole. Above the frequency 1/[C

], the series resistance and capacitance begin to look resistive

rather than capacitive, and the 90° phase shift and 20 dB/decade
contributed by C

no longer apply. Note that, to cancel the

load pole with the R

zero, the load pole must be known to

exist. Adding a zero to cancel a pole that does not exist causes
an oscillation (perhaps the expected load capacitor is not
present). Also, it is recommended to avoid creating a zero
frequency lower than the pole frequency; instead, allow the zero
frequency to be 2× or 3× higher than the calculated pole
frequency.

The Effect of R

can be used to ensure circuit stability when a poor load

capacitor with significant ESR is present. Above the frequency,
1/[C

× R

], the DUT begins to look resistive. The ESR of the

DUT capacitor, R

, contributes a zero at this frequency. The

load capacitor, C

, is counted on to stabilize the system when

the user has cancelled the load pole with the R

zero. Just as the

absence of C

under these circumstances can cause oscillations,

the presence of ESR R

while nonzero R

is used can cause