Техническая Спецификация для Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK

 806

SAM9M10 [DATASHEET]

6355F–ATARM–12-Mar-13

The high speed reset is managed by the hardware.

At the connection, the host makes a reset which could be a classic reset (full speed) or a high speed reset.

At the end of the reset process (full or high), the ENDRESET interrupt is generated.

Then the CPU should read the SPEED bit in UDPHS_INTSTAx to ascertain the speed mode of the device.

Interrupts are defined in 

 (UDPHS_IEN) and in 

Interrupts are enabled in UDPHS_IEN (see 

) and individually

.

Endpoint Interrupt Source Masks

SHRT_PCKT

Short Packet Interrupt

BUSY_BANK

Busy Bank Interrupt

NAK_OUT

NAKOUT Interrupt

NAK_IN/ERR_FLUSH

NAKIN/Error Flush Interrupt

STALL_SNT/ERR_CRISO/ERR_NB_TRA

Stall Sent/CRC error/Number of Transaction 
Error Interrupt

RX_SETUP/ERR_FL_ISO

Received SETUP/Error Flow Interrupt

TX_PK_RD /ERR_TRANS

TX Packet Read/Transaction Error Interrupt

TX_COMPLT

Transmitted IN Data Complete Interrupt

RX_BK_RDY

Received OUT Data Interrupt

ERR_OVFLW

Overflow Error Interrupt

MDATA_RX

MDATA Interrupt

DATAX_RX

DATAx Interrupt