Техническая Спецификация для Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

Enable bit in the Control register (CTRL.WEN) must be written to one and the Window Period bits in the Configuration 
register (CONFIG.WINDOW) must be defined.

On a power-on reset, some registers will be loaded with initial values from the NVM User Row. Refer to 

 for more details.

This encompasses the following bits and bit groups:

z

Enable bit in the Control register (CTRL.ENABLE)

z

Always-On bit in the Control register (CTRL.ALWAYSON)

z

Watchdog Timer Windows Mode Enable bit in the Control register (CTRL.WEN)

z

Watchdog Timer Windows Mode Time-Out Period bits in the Configuration register (CONFIG.WINDOW)

z

Time-Out Period in the Configuration register (CONFIG.PER)

z

Early Warning Interrupt Time Offset bits in the Early Warning Interrupt Control register (EWCTRL.EWOFFSET)

.

The WDT is enabled by writing a one to the Enable bit in the Control register (CTRL.ENABLE). The WDT is disabled by 
writing a zero to CTRL.ENABLE.

The WDT can be disabled only while the Always-On bit in the Control register (CTRL.ALWAYSON) is zero.

In normal-mode operation, the length of a time-out period is configured in CONFIG.PER. The WDT is enabled by writing 
a one to the Enable bit in the Control register (CTRL.ENABLE). Once enabled, if the WDT is not cleared from the 
application code before the time-out occurs, the WDT will issue a system reset. There are 12 possible WDT time-out 
(TO

WDT

) periods, selectable from 8ms to 16s, and the WDT can be cleared at any time during the time-out period. A new 

WDT time-out period will be started each time the WDT is cleared by writing 0xA5 to the Clear register (CLEAR - refer to 

). Writing any value other than 0xA5 to CLEAR will issue an immediate system reset.

By default, WDT issues a system reset upon a time-out, and the early warning interrupt is disabled. If an early warning 
interrupt is required, the Early Warning Interrupt Enable bit in the Interrupt Enable register (INTENSET.EW) must be 
enabled. Writing a one to the Early Warning Interrupt bit in the Interrupt Enable Set register (INTENSET.EW) enables the 
interrupt, and writing a one to the Early Warning Interrupt bit in the Interrupt Enable Clear register (INTENCLR.EW) 
disables the interrupt. If the Early Warning Interrupt is enabled, an interrupt is generated prior to a watchdog time-out 
condition. In normal mode, the Early Warning Offset bits in the Early Warning Interrupt Control register 
(EWCTRL.EWOFFSET) define the time where the early warning interrupt occurs. The normal-mode operation is 
illustrated in