Техническая Спецификация для Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO
Модели
ATSAMD20-XPRO
368
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
25.6.3 Additional Features
25.6.3.1 Address Recognition
When the SPI is configured for slave operation (CTRLA.MODE is 0x2) with address recognition (CTRLA.FORM is 0x2),
the SERCOM address recognition logic is enabled. When address recognition is enabled, the first character in a
transaction is checked for an address match. If there is a match, then the Receive Complete Interrupt flag in the Interrupt
Flag Status and Clear register (INTFLAG.RXC) is set, the MISO output is enabled and the transaction is processed. If
there is no match, the transaction is ignored.
the SERCOM address recognition logic is enabled. When address recognition is enabled, the first character in a
transaction is checked for an address match. If there is a match, then the Receive Complete Interrupt flag in the Interrupt
Flag Status and Clear register (INTFLAG.RXC) is set, the MISO output is enabled and the transaction is processed. If
there is no match, the transaction is ignored.
If the device is in sleep mode, an address match can wake up the device in order to process the transaction. If the
address does not match, then the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits
of the shift register are checked against the Address register (ADDR).
address does not match, then the complete transaction is ignored. If a 9-bit frame format is selected, only the lower 8 bits
of the shift register are checked against the Address register (ADDR).
for further details.
25.6.3.2 Preloading of the Slave Shift Register
When starting a transaction, the slave will first transmit the contents of the shift register before loading new data from
DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the
last reset) or the last character in the previous transmission. Preloading can be used to preload data to the shift register
while _SS is high and eliminate sending a dummy character when starting a transaction.
DATA. The first character sent can be either the reset value of the shift register (if this is the first transmission since the
last reset) or the last character in the previous transmission. Preloading can be used to preload data to the shift register
while _SS is high and eliminate sending a dummy character when starting a transaction.
In order to guarantee enough set-up time before the first SCK edge, enough time must be given between _SS going low
and the first SCK sampling edge, as shown in
and the first SCK sampling edge, as shown in
.
Preloading is enabled by setting the Slave Data Preload Enable bit in the Control B register (CTRLB.PLOADEN).
Figure 25-4. Timing Using Preloading
Only one data character written to DATA will be preloaded into the shift register while the synchronized _SS signal (see
) is high. The next character written to DATA before _SS is pulled low will be stored in DATA until transfer
begins. If the shift register is not preloaded, the current contents of the shift register will be shifted out.
25.6.3.3 Master with Several Slaves
If the bus consists of several SPI slaves, an SPI master can use general purpose I/O pins to control the _SS line to each
of the slaves on the bus, as shown in
of the slaves on the bus, as shown in
. In this configuration, the single selected SPI slave will drive the tri-
state MISO line.
_SS
Synchronization to
system domain
MISO to SCK
setup time
Required _SS to SCK time using
PRELOADEN
_SS synchronized to
system domain
SCK