Техническая Спецификация для Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO
Модели
ATSAMD20-XPRO
369
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
Figure 25-5. Multiple Slaves in Parallel
An alternate configuration is shown in
. In this configuration, all n attached slaves are connected in series. A
common _SS line is provided to all slaves, enabling them simultaneously. The master must shift n characters for a
complete transaction.
complete transaction.
Figure 25-6. Multiple Slaves in Series
25.6.3.4 Loop-back Mode
By configuring the Data In Pinout (CTRLA.DIPO) and Data Out Pinout (CTRLA.DOPO) to use the same data pins for
transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available externally.
transmit and receive, loop-back is achieved. The loop-back is through the pad, so the signal is also available externally.
25.6.4 Interrupts
The SPI has the following interrupt sources:
z
Receive Complete
z
Transmit Complete
z
Data Register Empty
Each interrupt source has an interrupt flag associated with it. The interrupt flag in the Interrupt Flag Status and Clear
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the SPI is reset. See the register description for details on how to clear interrupt flags.
register (INTFLAG) is set when the interrupt condition occurs. Each interrupt can be individually enabled by writing a one
to the corresponding bit in the Interrupt Enable Set register (INTENSET), and disabled by writing a one to the
corresponding bit in the Interrupt Enable Clear register (INTENCLR). An interrupt request is generated when the interrupt
flag is set and the corresponding interrupt is enabled. The interrupt request remains active until the interrupt flag is
cleared, the interrupt is disabled or the SPI is reset. See the register description for details on how to clear interrupt flags.
shift register
shift register
MOSI
MISO
MISO
SCK
_SS[0]
MOSI
MISO
_SS
SCK
shift register
MOSI
MISO
MISO
_SS
SCK
SPI Master
SPI Slave 0
_SS[n-1]
SPI Slave n-1
shift register
shift register
MOSI
MISO
MISO
SCK
_SS
MOSI
MISO
MISO
_SS
SCK
shift register
MOSI
MISO
MISO
_SS
SCK
SPI Master
SPI Slave 0
SPI Slave n-1