Техническая Спецификация для Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO

Модели
ATSAMD20-XPRO
Скачать
Страница из 660
437
Atmel | SMART SAM D20 [DATASHEET]
Atmel-42129K–SAM-D20_datasheet–06/2014
z
z
z
Period register (PER), 
z
Compare/Capture Value registers (CCx), 
Write-protection is denoted by the Write-Protection property in the register description. 
When the CPU is halted in debug mode, all write-protection is automatically disabled.
Write-protection does not apply for accesses through an external debugger. Refer to 
27.5.8 Analog Connections
Not applicable. 
27.6
Functional Description
27.6.1 Principle of Operation
The counter in the TC can be set to count on events from the Event System, or on the GCLK_TCx frequency. The pulses 
from GCLK_TCx will go through the prescaler, where it is possible to divide the frequency down. 
The value in the counter is passed to the compare/capture channels, where it can either be compared with user defined 
values or captured on a predefined event.
The TC can be configured as an 8-, 16- or 32-bit counter. Which mode is chosen will determine the maximum range of 
the counter. The counter range combined with the operating frequency will determine the maximum time resolution 
achievable with the TC peripheral.
The TC can be count up or down. By default, the counter will operate in a continuous mode and count up, where the 
counter will wrap to the zero when reaching the top value
When one of the compare/capture channels is used in compare mode, the TC can be used for waveform generation. 
Upon a match between the counter and the value in one or more of the Compare/Capture Value registers (CCx), one or 
more output pins on the device can be set to toggle. The CCx registers and the counter can thereby be used in frequency 
generation and PWM generation.
Capture mode can be used to automatically capture the period and pulse width of signals.
27.6.2 Basic Operation
27.6.2.1  Initialization
The following register is enable-protected, meaning that it can only be written when the TC is disabled (CTRLA.ENABLE 
is zero): 
z
), except the Run Standby (RUNSTDBY), Enable (ENABLE) and Software Reset 
(SWRST) bits
The following bits are enable-protected:
z
Event Action bits in the Event Control register (EVCTRL.EVACT)
Enable-protected bits in the CTRLA register can be written at the same time as CTRLA.ENABLE is written to one, but not 
at the same time as CTRLA.ENABLE is written to zero.
Before the TC is enabled, it must be configured, as outlined by the following steps:
z
The TC bus clock (CLK_TCx_APB) must be enabled
z
The mode (8, 16 or 32 bits) of the TC must be selected in the TC Mode bit group in the Control A register 
(CTRLA.MODE). The default mode is 16 bits
z
One of the wavegen modes must be selected in the Waveform Generation Operation bit group in the Control A 
register (CTRLA.WAVEGEN)