Техническая Спецификация для Atmel Xplained Pro Evaluation Kit ATSAMD20-XPRO ATSAMD20-XPRO

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Atmel | SMART SAM D20 [DATASHEET]

Atmel-42129K–SAM-D20_datasheet–06/2014

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If the GCLK_TCx frequency used should be prescaled, this can be selected in the Prescaler bit group in the 
Control A register (CTRLA.PRESCALER)

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If the prescaler is used, one of the presync modes must be chosen in the Prescaler and Counter Synchronization 
bit group in the Control A register (CTRLA.PRESYNC)

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One-shot mode can be selected by writing a one to the One-Shot bit in the Control B Set register 
(CTRLBSET.ONESHOT)

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If the counter should count down from the top value, write a one to the Counter Direction bit in the Control B Set 
register (CTRLBSET.DIR)

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If capture operations are to be used, the individual channels must be enabled for capture in the Capture Channel x 
Enable bit group in the Control C register (CTRLC.CPTEN)

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The waveform output for individual channels can be inverted using the Waveform Output Invert Enable bit group in 
the Control C register (CTRLC.INVEN)

The TC is enabled by writing a one to the Enable bit in the Control A register (CTRLA.ENABLE). The TC is disabled by 
writing a zero to CTRLA.ENABLE.

The TC is reset by writing a one to the Software Reset bit in the Control A register (CTRLA.SWRST). All registers in the 
TC, except DBGCTRL, will be reset to their initial state, and the TC will be disabled. Refer to the 

 register for 

details.

The TC should be disabled before the TC is reset to avoid undefined behavior.

As seen in 

, the GCLK_TC clock is fed into the internal prescaler. Prescaler output intervals from 1 to 1/1024 

are available. For a complete list of available prescaler outputs, see the register description for the Prescaler bit group in 
the Control A register (CTRLA.PRESCALER). 

The prescaler consists of a counter that counts to the selected prescaler value, whereupon the output of the prescaler 
toggles.

When the prescaler is set to a value greater than one, it is necessary to choose whether the prescaler should reset its 
value to zero or continue counting from its current value on the occurrence of an overflow or underflow. It is also 
necessary to choose whether the TC counter should wrap around on the next GCLK_TC clock pulse or the next 
prescaled clock pulse (CLK_TC_CNT of 

). To do this, use the Prescaler and Counter Synchronization bit 

group in the Control A register (CTRLA.PRESYNC).

If the counter is set to count events from the event system, these will not pass through the prescaler, as seen in 

.

The counter mode is selected with the TC Mode bit group in the Control A register (CTRLA.MODE). By default, the 
counter is enabled in the 16-bit counter mode.

Three counter modes are available:

EVENT

CNT

PRESCALER

PRESCALER

EVACT

GCLK_TC

GCLK_TC / 

{1,2,4,8,64,256,1024 }

CLK_TC_CNT