Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105

Модели

ATEVK1105

318

AT32UC3A

Figure 26-19.

FSK Modulator Output

26.7.4

Synchronous Receiver

In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of

the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity

bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode

operations provide a high speed transfer capability.
Configuration fields and bits are the same as in asynchronous mode.

illustrates a character reception in synchronous mode.

Figure 26-20.

Synchronous Mode Character Reception

26.7.4.1

Receiver Operations

When a character reception is completed, it is transferred to the Receive Holding Register

(RHR) and the RXRDY bit in the Status Register (CSR) rises. If a character is completed while

the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into

RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register

(CR) with the RSTSTA (Reset Status) bit at 1.

Manchester

encoded

data

default polarity

unipolar output

Txd

FSK Modulator

Output

Uptstream Frequencies

[F0, F0+offset]

NRZ stream

RXD

Start

Sampling

Parity Bit

Stop Bit

Example: 8-bit, Parity Enabled 1 Stop

Baud Rate

Clock

32058K

AVR32-01/12