Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
376
AT32UC3A
Figure 27-10.
No Setup, No Hold On NRD and NCS Read Signals
– Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to
unpredictable behavior.
27.6.4.2
Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
ings to know which signal rises first. The READ_MODE parameter in the MODE register of the
corresponding chip select indicates which signal of NRD and NCS controls the read operation.
– Read is Controlled by NRD (READ_MODE = 1):
shows the waveforms of a read operation of a typical asynchronous RAM. The
read data is available t
PACC
after the falling edge of NRD, and turns to ‘Z’ after the rising edge of
NRD. In this case, the READ_MODE must be set to 1 (read is controlled by NRD), to indicate
that data is available with the rising edge of NRD. The SMC samples the read data internally on
the rising edge of Master Clock that generates the rising edge of NRD, whatever the pro-
grammed waveform of NCS may be.
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
NRD_SETUP
NRD_PULSE
NCS_RD_PULSE
NRD_CYCLE
NRD_CYCLE
NCS_RD_PULSE
NCS_RD_PULSE
NRD_PULSE
NRD_CYCLE
32058K
AVR32-01/12