Техническая Спецификация для Atmel Evaluation Kit for AT32uC3A0512, 32-Bit AVR Microcontroller Atmel ATEVK1105 ATEVK1105
Модели
ATEVK1105
392
AT32UC3A
Figure 27-26.
TDF Mode = 0: TDF wait states between read and write accesses on the same chip select.
27.6.7
External Wait
Any access can be extended by an external device using the NWAIT input signal of the SMC.
The EXNW_MODE field of the MODE register on the corresponding chip select must be set to
either to “10” (frozen mode) or “11” (ready mode). When the EXNW_MODE is set to “00” (dis-
abled), the NWAIT signal is simply ignored on the corresponding chip select. The NWAIT signal
delays the read or write operation in regards to the read or write controlling signal, depending on
the read and write modes of the corresponding chip select.
27.6.7.1
Restriction
When one of the EXNW_MODE is enabled,
it is mandatory to program at least one hold
cycle for the read/write controlling signal. For that reason, the NWAIT signal cannot be
used in Page Mode (
used in Page Mode (
), or in Slow Clock Mode
(
).
The NWAIT signal is assumed to be a response of the external device to the read/write
request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the
read or write controlling signal. The assertion of the NWAIT signal outside the expected
period has no impact on SMC behavior.
request of the SMC. Then NWAIT is examined by the SMC only in the pulse state of the
read or write controlling signal. The assertion of the NWAIT signal outside the expected
period has no impact on SMC behavior.
CLK_SMC
A[25:2]
NBS0, NBS1,
A0, A1
Read1 controlling
signal(NRD)
Write2 controlling
signal(NWE)
D[15:0]
Read1 hold = 1
TDF_CYCLES = 5
Read1 cycle
TDF_CYCLES = 5
Read to Write
Wait State
4 TDF WAIT STATES
Write2 setup = 1
Write 2 cycle
TDF_MODE=0
(optimization disabled)
32058K
AVR32-01/12