Техническая Спецификация для Atmel ATmega328P Xplained Mini MEGA328P-XMINI MEGA328P-XMINI

105

ATmega48A/PA/88A/PA/168A/PA/328/P [DATASHEET]

Atmel-8271H-AVR- ATmega-Datasheet_08/2014

These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0 bits are set, the 
OC0A output overrides the normal port functionality of the I/O pin it is connected to. However, note that the Data 
Direction Register (DDR) bit corresponding to the OC0A pin must be set in order to enable the output driver.

When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM02:0 bit setting. 

 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to a normal or CTC mode 

(non-PWM).

 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM mode.

Note:

1.

A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Compare Match is 
ignored, but the set or clear is done at BOTTOM. See 

 for more details.

 shows the COM0A1:0 bit functionality when the WGM02:0 bits are set to phase correct PWM mode. 

Bit

7

6

5

4

3

2

1

0

Read/Write

R/W

R/W

R/W

R/W

R

R

R/W

R/W

Initial Value

0

0

0

0

0

0

0

0

0

0

Normal port operation, OC0A disconnected.

0

1

Toggle OC0A on Compare Match

1

0

Clear OC0A on Compare Match

1

1

Set OC0A on Compare Match

0

0

Normal port operation, OC0A disconnected.

0

1

WGM02 = 0: Normal Port Operation, OC0A Disconnected.
WGM02 = 1: Toggle OC0A on Compare Match.

1

0

Clear OC0A on Compare Match, set OC0A at BOTTOM,
(non-inverting mode).

1

1

Set OC0A on Compare Match, clear OC0A at BOTTOM,
(inverting mode).