Техническая Спецификация для STMicroelectronics Evaluation board for A5970AD EVALA5970AD EVALA5970AD

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DocID14661 Rev 5

An internal block continuously senses the V

cc

, V

ref

 and V

bg

. If the voltages go higher than 

their thresholds, the regulator begins operating. There is also a hysteresis on the V

CC

 

(UVLO).

 shows the block diagram of the oscillator circuit.

The clock generator provides the switching frequency of the device, which is internally fixed 
at 500 kHz. The frequency shifter block acts to reduce the switching frequency in case of 
strong overcurrent or short-circuit. The clock signal is then used in the internal logic circuitry 
and is the input of the ramp generator and synchronizer blocks.

The ramp generator circuit provides the sawtooth signal, used for PWM control and the 
internal voltage feed-forward, while the synchronizer circuit generates the synchronization 
signal. The device also has a synchronization pin which can work both as master and slave.

Beating frequency noise is an issue when more than one voltage rail is on the same board. 
A simple way to avoid this issue is to operate all the regulators at the same switching 
frequency. 

The synchronization feature of a set of the A5970AD is simply get connecting together their 
SYNCH pin. The device with highest switching frequency will be the MASTER and it 
provides the synchronization signal to the others. Therefore the SYNCH is a I/O pin to 
deliver or recognize a frequency signal. The synchronization circuitry is powered by the 
internal reference (V

REF

) so a small filtering capacitor (

100 nF) connected between V

REF

 

pin and the signal ground of the master device is suggested for its proper operation. 
However when a set of synchronized devices populates a board it is not possible to know in 
advance the one working as master, so the filtering capacitor have to be designed for whole 
set of devices.

When one or more devices are synchronized to an external signal, its amplitude have to be 
in comply with specifications given in the 

. The frequency of the 

synchronization signal must be, at a minimum, higher than the maximum guaranteed natural 
switching frequency of the device (575 kHz, see 

) while the duty cycle of the 

synchronization signal can vary from approximately 10% to 90%. The small capacitor under 
V

REF

 pin is required for this operation.