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4538 Hardware Reference Manual

vii

List of Tables

........................................................................................................................5

Table 1-2.

Local Interrupts

........................................................................................................................................7

Table 1-3.

PowerQUICC II Memory Controller Machine Usage

.............................................................................7

Table 1-4.

CPM Port A Usage

...................................................................................................................................8

Table 1-5.

CPM Port B Usage

...................................................................................................................................8

Table 1-6.

CPM Port C Usage

...................................................................................................................................9

Table 1-7.

CPM Port D Usage

...................................................................................................................................9

Table 1-8.

CPM SI1 TDM Busses Wiring

...............................................................................................................10

Table 1-9.

CPM SI2 TDM Busses Wiring

...............................................................................................................10

Table 1-10. CPM Bank of Clocks Usage

...................................................................................................................11

Table 1-11. CPM Baud Rate Usage

...........................................................................................................................11

Table 1-12. Ethernet Signals on the CPM

.................................................................................................................11

Table 1-13. Asynchronous Console Serial Port Wiring

............................................................................................12

Table 1-14. User-Programmable LED Control Ports

................................................................................................13

Table 1-15. PCI Configuration Registers

..................................................................................................................14

Table 1-16. PowerSpan PCI Registers

.......................................................................................................................15

Table 1-17. PowerSpan Processor Bus Registers

......................................................................................................16

Table 1-18. PowerSpan DMA Registers

...................................................................................................................17

Table 1-19. PowerSpan Miscellaneous Registers

......................................................................................................18

Table 1-20. PowerSpan I²O Registers

.......................................................................................................................19

Table 1-21. PowerSpan Interrupt Pin Usage

.............................................................................................................20

Table 1-22. Serial EEPROM Mapping

......................................................................................................................27

Table 1-23. Board Equipment Register Layout

.........................................................................................................27

Table 1-24. Hardware Configuration Register Field Descriptions

............................................................................28

Table 1-25. FLASH EEPROM Mapping

...................................................................................................................29

Table 1-26. GCM Register Programming (MCLK=12.500 MHz)

............................................................................31

Table 1-27. Transmit Pulse Shape Programming

......................................................................................................31

Table 1-28. QuadFALC Multifunction Port Usage

...................................................................................................32

Table 1-29. Ethernet LEDs

........................................................................................................................................33

Table 1-30. TDM and Synchronization Signals in Multiplex Direct Mode

..............................................................38

Table 1-31. TDM and Synchronization Signals in Independent Direct Mode

..........................................................42

Table 1-32. TDM and Synchronization Signals in Switched Mode

..........................................................................48

Table 1-33. TDM and Synchronization Signals in Pass Through Mode

...................................................................52

Table 2-1.

PowerSpan Register Initialization Values in the Serial EEPROM

........................................................60

Table 2-2.

PowerQUICC II Memory Controller Machine Usage

...........................................................................65

Table 2-3.

CPM Port Register initialization Values

................................................................................................67

Table 3-1.

GCM Register Programming

.................................................................................................................75

Table 3-2.

Channel Phase Programming in Multiplexed System Data Streams

.....................................................77

Table 3-3.

QuadFALC RCLK Reference Source for DCO-R

.................................................................................77

Table 3-4.

Common T1/E1/E1-CRC4 Initialization

...............................................................................................82

Table 3-5.

T1 Specific Initialization

........................................................................................................................82

Table 3-6.

E1/E1-CRC4 Common Initialization

.....................................................................................................82

Table 3-7.

E1 Non-CRC4 Specific Initialization

.....................................................................................................83

Table 3-8.

E1-CRC4 Specific Initialization.

............................................................................................................83

Table 3-9.

Slave Mode Initialization

.......................................................................................................................83

Table 3-10. Master Mode Initialization

.....................................................................................................................83

Table 5-1.

RJ48 Connectors J1 and J2

.....................................................................................................................97

Table 5-2.

Ethernet 10/100 RJ45 Connector

...........................................................................................................97