Справочник Пользователя для Intel Core™ i5-750 Processor (8M Cache, 2.66 GHz) BX8060515750
Модели
BX8060515750
Datasheet, Volume 2
221
Processor Uncore Configuration Registers
4.7.2
MC_SMI_DIMM_ERROR_STATUS
SMI DIMM error threshold overflow status register. This bit is set when the per-DIMM
error counter exceeds the specified threshold. The bit is reset by BIOS.
error counter exceeds the specified threshold. The bit is reset by BIOS.
4.7.3
MC_SMI_CNTRL
System Management Interrupt control register.
Device:
3
Function: 0
Offset:
50h
Access as a DWord
Bit
Type
Default
Description
31:14
RO
0
Reserved
13:12
RW0C
0
REDUNDANCY_LOSS_FAILING_DIMM
The ID for the failing DIMM when redundancy is lost.
The ID for the failing DIMM when redundancy is lost.
11:8
Reserved
7:0
RW0C
0
DIMM_ERROR_OVERFLOW_STATUS
This 8-bit field is the per DIMM error overflow status bits. The organization is as
This 8-bit field is the per DIMM error overflow status bits. The organization is as
follows:
If there are one or two DIMMS on the channel:
Bit 0 = DIMM 0, Ranks 0 and 1, Channel 0
Bit 1 = DIMM 0, Ranks 2 and 3, Channel 0
Bit 2 = DIMM 1, Ranks 0 and 1, Channel 0
Bit 3 = DIMM 1, Ranks 2 and 3, Channel 0
Bit 4 = DIMM 0, Ranks 0 and 1, Channel 1
Bit 5 = DIMM 0, Ranks 2 and 3, Channel 1
Bit 6 = DIMM 1, Ranks 0 and 1, Channel 1
Bit 7 = DIMM 1, Ranks 2 and 3, Channel 1
If there are one or two DIMMS on the channel:
Bit 0 = DIMM 0, Ranks 0 and 1, Channel 0
Bit 1 = DIMM 0, Ranks 2 and 3, Channel 0
Bit 2 = DIMM 1, Ranks 0 and 1, Channel 0
Bit 3 = DIMM 1, Ranks 2 and 3, Channel 0
Bit 4 = DIMM 0, Ranks 0 and 1, Channel 1
Bit 5 = DIMM 0, Ranks 2 and 3, Channel 1
Bit 6 = DIMM 1, Ranks 0 and 1, Channel 1
Bit 7 = DIMM 1, Ranks 2 and 3, Channel 1
Device:
3
Function: 0
Offset:
54h
Access as a DWord
Bit
Type
Default
Description
31:17
RO
0
Reserved
16
RW
0
INTERRUPT_SELECT_NMI. NMI Enable
This bit is set to enable NMI signaling. Clear to disable NMI signaling. If both
This bit is set to enable NMI signaling. Clear to disable NMI signaling. If both
NMI and SMI enable bits are set, then only SMI is sent.
15
RW
0
INTERRUPT_SELECT_SMI. SMI Enable.
This bit is set to enable SMI signaling. Clear to disable SMI signaling. If both
This bit is set to enable SMI signaling. Clear to disable SMI signaling. If both
NMI and SMI enable bits are set, then only SMI is sent.
14:0
RW
0
Reserved