Справочник Пользователя для Intel Core™ i5-750 Processor (8M Cache, 2.66 GHz) BX8060515750
Модели
BX8060515750
Processor Uncore Configuration Registers
222
Datasheet, Volume 2
4.7.4
MC_STATUS
MC Primary Status register.
4.7.5
MC_RESET_CONTROL
DIMM Reset enabling controls.
Device:
3
Function: 0
Offset:
4Ch
Access as a DWord
Bit
Attr
Default
Description
31:17
RO
0
Reserved
4
RO
1
Reserved
3
RO
0
Reserved
2
RO
0
Reserved
1
RO
0
CHANNEL1_DISABLED. Channel 1 is disabled.
This can be factory configured or if Init done is written without the
This can be factory configured or if Init done is written without the
channel_active being set. Clocks in the channel will be disabled when this bit
is set.
0
RO
0
CHANNEL0_DISABLED. Channel 0 is disabled.
This can be factory configured or if Init done is written without the
This can be factory configured or if Init done is written without the
channel_active being set. Clocks in the channel will be disabled when this bit
is set.
Device:
3
Function: 0
Offset:
5Ch
Access as a DWord
Bit
Attr
Default
Description
31:1
RO
0
Reserved
0
WO
0
BIOS_RESET_ENABLE
When set, MC takes over control of driving RESET to the DIMMs. This bit is
When set, MC takes over control of driving RESET to the DIMMs. This bit is
set on S3 exit and cold boot to take over RESET driving responsibility from
the physical layer.