Справочник Пользователя для Mitsubishi Electronics FX2NC
FX Series Programmable Controlers
Applied Instructions 5
5-31
5.3.9
WXOR (FNC 28)
Operation:
The bit patterns of the two source devices are
analyzed (the contents of S
analyzed (the contents of S
2
is compared against
the contents of S
1
). The result of the logical XOR
analysis is stored in the destination device (D).
The following rules are used to determine the result of a logical XOR operation. This takes
place for every bit contained within the source devices:
General rule: (S
place for every bit contained within the source devices:
General rule: (S
1
)Bit
n
WXOR (S
2
)Bit
n
= (D)Bit
n
1 WXOR 1 = 0
0 WXOR 1 = 1
1 WXOR 0 = 1
0 WXOR 0 = 0
5.3.10
NEG (FNC 29)
Operation:
The bit pattern of the selected device is inverted.
This means any occurrence of a ‘1’ becomes a ‘0’
and any occurrence of a ‘0’ will be written as a ‘1’.
This means any occurrence of a ‘1’ becomes a ‘0’
and any occurrence of a ‘0’ will be written as a ‘1’.
When this is complete, a further binary 1 is added to the bit pattern. The result is the total
logical sign change of the selected devices contents, e.g. a positive number will become a
negative number or a negative number will become a positive.
logical sign change of the selected devices contents, e.g. a positive number will become a
negative number or a negative number will become a positive.
Mnemonic
Function
Operands
Program steps
S1
S2
D
WXOR
FNC 28
(Logical
exclusive
OR)
FNC 28
(Logical
exclusive
OR)
A logical XOR is
performed on the
source devices -
result stored at
destination
performed on the
source devices -
result stored at
destination
K, H
KnX, KnY, KnM, KnS,
T, C, D, V, Z
KnX, KnY, KnM, KnS,
T, C, D, V, Z
KnY, KnM, KnS,
T, C, D, V, Z
T, C, D, V, Z
WXOR,
WXORP:
7 steps
DXOR,DXORP
13 steps
WXORP:
7 steps
DXOR,DXORP
13 steps
Mnemonic
Function
Operands
Program steps
D
NEG
FNC 29
(Negation)
FNC 29
(Negation)
Logically inverts
the contents of
the designated
device
the contents of
the designated
device
KnY, KnM, KnS,
T, C, D, V, Z
T, C, D, V, Z
NEG,NEGP:
3 steps
DNEG,
DNEGP:
5 steps
3 steps
DNEG,
DNEGP:
5 steps
FX
0(S)
FX
0N
FX FX
(2C)
FX
2N(C)
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
PULSE-P
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
16 BIT OPERATION
FX
FX
0N
FX
0(s)
FX
(2C)
FX
2N(C)
32 BIT OPERATION
X2
WXOR D 10 D 12 D 14
[ S1 ]
[ D ]
[ S2 ]
FX
0(S)
FX
0N
FX FX
(2C)
FX
2N(C)
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
PULSE-P
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
16 BIT OPERATION
FX
FX
0N
FX
0(s)
FX
(2C)
FX
2N(C)
32 BIT OPERATION
X0
[ D ]
D 10
NEG