Справочник Пользователя для Mitsubishi Electronics FX2NC

Скачать
Страница из 382
FX Series Programmable Controlers
Applied Instructions 5
5-38
5.4.7
WSFR (FNC 36)
Operation:
The instruction copies n
source devices to a word
stack of length n
1
. For each addition of n
2
words, the
existing data within the word stack is shifted n
2
words
to the right. Any word data moving to a position
exceeding the n
1
limit is diverted to an overflow area.
The word shifting operation will occur every time the
instruction is processed unless it is modified with
either the pulse suffix or a controlled interlock.
Note: when using bit devices as source (S) and
destination (D) the Kn value must be equal.
5.4.8
WSFL (FNC 37)
Operation:
The instruction copies n
source devices to a word
stack of length n
1
. For each addition of n
2
words, the
existing data within the word stack is shifted n
2
words
to the left. Any word data moving to a position
exceeding the n
limit is diverted to an overflow area.
The word shifting operation will occur every time the
instruction is processed unless it is modified with
either the pulse suffix or a controlled interlock.
Note: when using bit devices as source (S) and
destination (D) the Kn value must be equal.
Mnemonic
Function 
Operands
Program steps
S
D
n
1
n
2
WSFR
FNC 36
(
Word
shift right)
The value of the
source devices are
copied to a
controlled word 
stack moving the
existing data to the 
right
KnX, KnY,
KnM,KnS,
T, C, D
KnY,KnM,
KnS,
T, C, D
K,H,
Note:
FX users: n
≤ 
n
≤ 
512
WSFR,
WSFRP:
9 steps
Mnemonic
Function 
Operands
Program steps
S
D
n
1
n
2
WSFL
FNC 37
(
Word 
shift left)
The value of the
source devices are
copied to a
controlled word 
stack moving the
existing data to 
the left
KnX, KnY,
KnM,KnS,
T, C, D
KnY,KnM,
KnS,
T, C, D
K,H,
Note:
FX users: 
n
≤ 
n
≤ 
512
WSFL,
WSFLP:
9 steps
FX
0(S)
FX
0N
FX FX
(2C)
FX
2N(C)
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
PULSE-P
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
16 BIT OPERATION
FX
FX
0N
FX
0(s)
FX
(2C)
FX
2N(C)
32 BIT OPERATION
X0
WSFR 
D 10 K 16
K 4
[ S ]
[ D ]
D 0
[ n1 ] [ n2 ]
(1)
(2)
(3)
(4)
(5)
D
D
D
D
D
(1)
(2)
(3)
(4)
(5)
13
17
21
25
3
-
-
-
-
-
D
D
D
D
D
10
14
18
22
0
D
D
D
D
13
17
21
25
-
-
-
-
D
D
D
D
10
14
18
22
D 3
D 2
D 1
D 0
D25 D24 D23 D22
D18
D21
D14
D17
D13 D12 D11 D10
FX
0(S)
FX
0N
FX FX
(2C)
FX
2N(C)
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
PULSE-P
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
16 BIT OPERATION
FX
FX
0N
FX
0(s)
FX
(2C)
FX
2N(C)
32 BIT OPERATION
X0
WSFR 
D 10 K 16
K 4
[ S ]
[ D ]
D 0
[ n1 ] [ n2 ]
(5)
(1)
(2)
(3)
(4)
D
D
D
D
D
(1)
(2)
(3)
(4)
(5)
25
21
17
13
3
-
-
-
-
-
D
D
D
D
D
D
D
D
D
25
21
17
13
-
-
-
-
D
D
D
D
22
18
14
10
22
18
14
10
0
D 3
D 2
D 1
D 0
D13 D12 D11 D10
D14
D17
D18
D21
D25 D24 D23 D22