Справочник Пользователя для Mitsubishi Electronics FX2NC
FX Series Programmable Controlers
Applied Instructions 5
5-40
5.4.10
SFRD (FNC 39)
Operation:
The source device (S) identifies the head address
of the FIFO stack. Its contents reflect the last entry
point of data on to the FIFO stack, i.e. where the
end of the FIFO is (current position).
This instruction reads the first piece of data from
the FIFO stack (register S
of the FIFO stack. Its contents reflect the last entry
point of data on to the FIFO stack, i.e. where the
end of the FIFO is (current position).
This instruction reads the first piece of data from
the FIFO stack (register S
+1
), moves all of the data
within the stack ‘up’ one position to fill the read
area and decrements the contents of the FIFO
head address (S) by 1. The read data is written to
the destination device (D).
When the contents of the source device (S) are
equal to ‘0’ (zero), i.e. the FIFO stack is empty, the
flag M8020 is turned ON.
area and decrements the contents of the FIFO
head address (S) by 1. The read data is written to
the destination device (D).
When the contents of the source device (S) are
equal to ‘0’ (zero), i.e. the FIFO stack is empty, the
flag M8020 is turned ON.
Points to note:
a) FIFO is an abbreviation for ‘First-In/ First-OUT’.
b) Only n
-1
pieces of data may be read from a FIFO stack. This is because the stack requires
that the first register, the head address (S) is used to contain information about the current
length of the FIFO stack.
length of the FIFO stack.
c) This instruction will always read the source data from the register S
+1
.
d) This instruction should be used in conjunction with SFWR FNC 38. The n parameter in both
instructions should be equal.
Mnemonic
Function
Operands
Program steps
S
D
n
SFRD
FNC 39
(Shift
register read)
FNC 39
(Shift
register read)
This instruction
reads and
reduces FIFO
stack- must be
used with SFWR
FNC 38
reads and
reduces FIFO
stack- must be
used with SFWR
FNC 38
KnY, KnM,
KnS,
T, C, D,
KnY,
KnM,KnS,
T, C, D
KnS,
T, C, D,
KnY,
KnM,KnS,
T, C, D
KnY, KnM,
KnS,
T, C, D,
KnY,
KnM,KnS,
T, C, D, V, Z
KnS,
T, C, D,
KnY,
KnM,KnS,
T, C, D, V, Z
K,H,
Note:
2
2
≤
n
≤
512
SFRD,
SFRDP:
7 steps
SFRDP:
7 steps
FX
0(S)
FX
0N
FX FX
(2C)
FX
2N(C)
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
PULSE-P
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
16 BIT OPERATION
FX
FX
0N
FX
0(s)
FX
(2C)
FX
2N(C)
32 BIT OPERATION
FLAGS Zero M8020
X1
SFRD
D 20 K 10
[ S ]
[ D ]
D 1
[ n ]
D 20
D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1
[D]
= 10
[n]