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Trip-Zone Submodule Control and Status Registers
Table 4-19. Trip-Zone Enable Interrupt Register (TZEINT) Field Descriptions (continued)
Bits
Name
Value
Description
1
Enable Interrupt generation; a one-shot trip event will cause a EPWMx_TZINT PIE interrupt.
(1)
1
CBC
Trip-zone Cycle-by-Cycle Interrupt Enable
0
Disable cycle-by-cycle interrupt generation.
1
Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE
interrupt.
interrupt.
(1)
0
Reserved
Reserved
(1)
The Peripheral Interrupt Expansion (PIE) module is described in the specific device version of the System Control and Interrupts
Reference Guide listed in
Reference Guide listed in
Section 1
.
Figure 4-20. Trip-Zone Flag Register (TZFLG)
15
8
Reserved
R-0
7
3
2
1
0
Reserved
OST
CBC
INT
R-0
R-0
R-0
R-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-20. Trip-Zone Flag Register (TZFLG) Field Descriptions
Bits
Name
Value Description
15-3
Reserved
Reserved
2
OST
Latched Status Flag for A One-Shot Trip Event
0
No one-shot trip event has occurred.
1
Indicates a trip event has occurred on a pin selected as a one-shot trip source.
This bit is cleared by writing the appropriate value to the TZCLR register (
).
1
CBC
Latched Status Flag for Cycle-By-Cycle Trip Event
0
No cycle-by-cycle trip event has occurred.
1
Indicates a trip event has occurred on a pin selected as a cycle-by-cycle trip source. The
TZFLG[CBC] bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip
event is still present when the CBC bit is cleared, then CBC will be immediately set again. The
specified condition on the pins is automatically cleared when the ePWM time-base counter
reaches zero (TBCTR = 0x0000) if the trip condition is no longer present. The condition on the
pins is only cleared when the TBCTR = 0x0000 no matter where in the cycle the CBC flag is
cleared.
TZFLG[CBC] bit will remain set until it is manually cleared by the user. If the cycle-by-cycle trip
event is still present when the CBC bit is cleared, then CBC will be immediately set again. The
specified condition on the pins is automatically cleared when the ePWM time-base counter
reaches zero (TBCTR = 0x0000) if the trip condition is no longer present. The condition on the
pins is only cleared when the TBCTR = 0x0000 no matter where in the cycle the CBC flag is
cleared.
This bit is cleared by writing the appropriate value to the TZCLR register (
).
0
INT
Latched Trip Interrupt Status Flag
0
Indicates no interrupt has been generated.
1
Indicates an EPWMx_TZINT PIE interrupt was generated because of a trip condition.
No further EPWMx_TZINT PIE interrupts will be generated until this flag is cleared. If the
interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be
generated. Clearing all flag bits will prevent further interrupts.
interrupt flag is cleared when either CBC or OST is set, then another interrupt pulse will be
generated. Clearing all flag bits will prevent further interrupts.
This bit is cleared by writing the appropriate value to the TZCLR register (
).
SPRU791D – November 2004 – Revised October 2007
Registers
109