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Event-Trigger Submodule Registers
Figure 4-23. Event-Trigger Selection Register (ETSEL)
15
14
12
11
10
8
SOCBEN
SOCBSEL
SOCAEN
SOCASEL
R/W-0
R/W-0
R/W-0
R/W-0
7
4
3
2
0
Reserved
INTEN
INTSEL
R-0
R/W-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descriptions
Bits
Name
Value
Description
15
SOCBEN
Enable the ADC Start of Conversion B (EPWMxSOCB) Pulse
0
Disable EPWMxSOCB.
1
Enable EPWMxSOCB pulse.
14-12
SOCBSEL
EPWMxSOCB Selection Options
These bits determine when a EPWMxSOCB pulse will be generated.
000
Reserved
001
Enable event time-base counter equal to zero. (TBCTR = 0x0000)
010
Enable event time-base counter equal to period (TBCTR = TBPRD)
011
Reserved
100
Enable event time-base counter equal to CMPA when the timer is incrementing.
101
Enable event time-base counter equal to CMPA when the timer is decrementing.
110
Enable event: time-base counter equal to CMPB when the timer is incrementing.
111
Enable event: time-base counter equal to CMPB when the timer is decrementing.
11
SOCAEN
Enable the ADC Start of Conversion A (EPWMxSOCA) Pulse
0
Disable EPWMxSOCA.
1
Enable EPWMxSOCA pulse.
10-8
SOCASEL
EPWMxSOCA Selection Options
These bits determine when a EPWMxSOCA pulse will be generated.
000
Reserved
001
Enable event time-base counter equal to zero. (TBCTR = 0x0000)
010
Enable event time-base counter equal to period (TBCTR = TBPRD)
011
Reserved
100
Enable event time-base counter equal to CMPA when the timer is incrementing.
101
Enable event time-base counter equal to CMPA when the timer is decrementing.
110
Enable event: time-base counter equal to CMPB when the timer is incrementing.
111
Enable event: time-base counter equal to CMPB when the timer is decrementing.
7-4
Reserved
Reserved
3
INTEN
Enable ePWM Interrupt (EPWMx_INT) Generation
0
Disable EPWMx_INT generation
1
Enable EPWMx_INT generation
SPRU791D – November 2004 – Revised October 2007
Registers
111