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Event-Trigger Submodule Registers
Table 4-23. Event-Trigger Selection Register (ETSEL) Field Descriptions (continued)
Bits
Name
Value
Description
2-0
INTSEL
ePWM Interrupt (EPWMx_INT) Selection Options
000
Reserved
001
Enable event time-base counter equal to zero. (TBCTR = 0x0000)
010
Enable event time-base counter equal to period (TBCTR = TBPRD)
011
Reserved
100
Enable event time-base counter equal to CMPA when the timer is incrementing.
101
Enable event time-base counter equal to CMPA when the timer is decrementing.
110
Enable event: time-base counter equal to CMPB when the timer is incrementing.
111
Enable event: time-base counter equal to CMPB when the timer is decrementing.
Figure 4-24. Event-Trigger Prescale Register (ETPS)
15
14
13
12
11
10
9
8
SOCBCNT
SOCBPRD
SOCACNT
SOCAPRD
R-0
R/W-0
R-0
R/W-0
7
4
3
2
1
0
Reserved
INTCNT
INTPRD
R-0
R-0
R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 4-24. Event-Trigger Prescale Register (ETPS) Field Descriptions
Bits
Name
Description
15-14
SOCBCNT
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Counter Register
These bits indicate how many selected ETSEL[SOCBSEL] events have occurred:
00
No events have occurred.
01
1 event has occurred.
10
2 events have occurred.
11
3 events have occurred.
13-12
SOCBPRD
ePWM ADC Start-of-Conversion B Event (EPWMxSOCB) Period Select
These bits determine how many selected ETSEL[SOCBSEL] events need to occur before an
EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled
(ETSEL[SOCBEN] = 1). The SOCB pulse will be generated even if the status flag is set from
a previous start of conversion (ETFLG[SOCB] = 1). Once the SOCB pulse is generated, the
ETPS[SOCBCNT] bits will automatically be cleared.
EPWMxSOCB pulse is generated. To be generated, the pulse must be enabled
(ETSEL[SOCBEN] = 1). The SOCB pulse will be generated even if the status flag is set from
a previous start of conversion (ETFLG[SOCB] = 1). Once the SOCB pulse is generated, the
ETPS[SOCBCNT] bits will automatically be cleared.
00
Disable the SOCB event counter. No EPWMxSOCB pulse will be generated
01
Generate the EPWMxSOCB pulse on the first event: ETPS[SOCBCNT] = 0,1
10
Generate the EPWMxSOCB pulse on the second event: ETPS[SOCBCNT] = 1,0
11
Generate the EPWMxSOCB pulse on the third event: ETPS[SOCBCNT] = 1,1
11-10
SOCACNT
ePWM ADC Start-of-Conversion A Event (EPWMxSOCA) Counter Register
These bits indicate how many selected ETSEL[SOCASEL] events have occurred:
00
No events have occurred.
01
1 event has occurred.
10
2 events have occurred.
11
3 events have occurred.
112
Registers
SPRU791D – November 2004 – Revised October 2007