Справочник Пользователя для Fujitsu mb91192
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Appendix E Instruction List
■
Bit Manipulation Instructions
■
Multiplication and Division Instructions
Table E-6 Bit manipulation instructions
Mnemonic
Type
OP CYCLE NZVC
Operation
Remark
BANDL #u4, @Ri
BANDH #u4, @Ri
*BAND #u8, @Ri
BANDH #u4, @Ri
*BAND #u8, @Ri
*1
C
C
C
80
81
81
1+2a
1+2a
1+2a
----
----
----
----
----
(Ri) &=(0xF0+u4)
(Ri) &=((u4 < <4)+0x0F)
(Ri) &=u8
(Ri) &=((u4 < <4)+0x0F)
(Ri) &=u8
The subordinate position four bits are
operated.
The high rank four bits are operated.
operated.
The high rank four bits are operated.
BORL #u4, @Ri
BORH #u4, @Ri
*BOR #u8, @Ri
BORH #u4, @Ri
*BOR #u8, @Ri
*2
C
C
C
90
91
91
1+2a
1+2a
1+2a
----
----
----
----
----
(Ri) | =u4
(Ri) | =(u4 < <4)
(Ri) | =u8
(Ri) | =(u4 < <4)
(Ri) | =u8
The subordinate position four bits are
operated.
The high rank four bits are operated.
operated.
The high rank four bits are operated.
BEORL #u4, @Ri
BEORH #u4, @Ri
*BEOR #u8, @Ri
BEORH #u4, @Ri
*BEOR #u8, @Ri
*3
C
C
C
98
99
99
1+2a
1+2a
1+2a
----
----
----
----
----
(Ri) ^ =u4
(Ri) ^ =(u4 < <4)
(Ri) ^ =u8
(Ri) ^ =(u4 < <4)
(Ri) ^ =u8
The subordinate position four bits are
operated.
The high rank four bits are operated.
operated.
The high rank four bits are operated.
BTSTL #u4, @Ri
BTSTH #u4, @Ri
BTSTH #u4, @Ri
C
C
C
88
89
89
2+a
2+a
2+a
0C--
CC--
(Ri) &u4
(Ri) &(u4 < <4)
(Ri) &(u4 < <4)
Lower 4 bit test
Upper 4 bit test
Upper 4 bit test
*1: The assembler generates BANDL when the u8&0x0F bit is raised, or generates BANDH when the u8&0xF0 bit is raised. There is a
case generating both BANDL and BANDH.
*2: The assembler generates BORL when the u8&0x0F bit is raised, or generates BORH when the u8&0xF0 bit is raised. There is a case
generating both BORL and BODH.
*3: The assembler generates BEORL when the u8&0x0F bit is raised, or generates BEORH when the u8&0xF0 bit is raised. There is a
case generating both BEORL and BEORH.
Table E-7 Multiplication and division instructions
Mnemonic
Type
OP CYCLE NZVC
Operation
Remark
MUL Rj,Ri
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
A
A
A
A
A
A
A
AF
AB
BF
BB
5
5
3
3
5
3
3
CCC-
CCC-
CCC-
CC--
CC--
CC--
Ri*Rj
→
MDH,MDL
Ri*Rj
→
MDH,MDL
Ri*Rj
→
MDL
Ri*Rj
→
MDL
32bit*32bit=64bit
None
16bit*16bit=32bit
None
None
16bit*16bit=32bit
None
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
*DIV Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
*DIV Ri
*1
*DIVU Ri
*2
E
E
E
E
E
E
E
E
E
E
E
97-4
97-5
97-6
97-7
9F-6
9F-7
97-5
97-6
97-7
9F-6
9F-7
1
1
d
1
1
1
1
d
1
1
1
36
33
----
----
----
-C-C
-C-C
-C-C
----
----
----
-C-C
-C-C
MDL/Ri
→
MDL,
MDL%Ri
→
MDH
MDL/Ri
→
MDL,
MDL%Ri
→
MDH
Step operation
32bit/32bit=32bit
32bit/32bit=32bit
*1:Generates DIV0S, DIV1
×
32, DIV2, DIV3, DIV4S. Instruction code length is 72 bytes.
*2:Generates DIV0U, DIV1
×
32. Instruction code length is 66 bytes.