Справочник ПользователяСодержаниеCHAPTER 1 Overview of MB91191/ MB91192 Series151.1 Feature of MB91191/MB91192 Series161.2 Block Diagram of All MB91191/MB91192 Series181.3 Package Dimension191.4 Pin Assignment211.5 Pin Function Description231.6 I/O Circuit Type29CHAPTER 2 Handling Devices312.1 Precautions When Handling Devices322.2 Others36CHAPTER 3 CPU373.1 Memory Space383.2 CPU Architecture403.3 Dedicated Registers433.3.1 Program Status Register (PS)463.4 General-purpose Register503.5 Data Construction513.6 Word Alignment523.7 Memory Map533.8 Overview of Instructions543.8.1 Branch Command with Delay Slot563.8.2 Branch Command without Delay Slot583.9 EIT (Exception, Interruption, and Trap)593.9.1 Interrupt Level of EIT603.9.2 Interrupt Stack Operation613.9.3 EIT Vector Table623.9.4 Multiple EIT Processing633.9.5 Operation of EIT653.10 Reset Sequence693.11 Memory Access Mode703.12 Clock Generation Section (Low Power Consumption Mechanism)733.12.1 Reset Factor Register (RSRR) and Watchdog Timer Cycle Control Register (WTCR)753.12.2 Standby Control Register (STCR)773.12.3 Timebase Timer Clear Register (CTBR)783.12.4 Gear Control Register (GCR)793.12.5 Watchdog Reset Generation Delay Register (WPR)813.12.6 Reset Factor Retention823.12.7 Stop Status843.12.8 Sleep Status873.12.9 State Transition in Standby Mode903.12.10 Gear Function913.12.11 Clock Series Diagram943.12.12 Clock Series of Peripheral Resource953.12.13 Watchdog Function96CHAPTER 4 External Bus Interface994.1 Overview of External Bus Interface1004.2 Block Diagram1014.3 Area of Bus Interface1024.4 Bus Interface1034.5 Register of External bus Interface1044.5.1 Area Selection Register (ASR) and Area Mask Register (AMR)1054.5.2 Area Mode Register 1 (AMD1)1084.5.3 Little Endian Register (LER)1104.6 Bus Operation1114.6.1 Relationship between Data Bus Width and Control Signal1124.6.2 Bus Access of Big Endian1134.6.3 Bus Access of Little Endian1184.6.4 Comparison between Big Endian and Little Endian for External Access1224.7 Bus Timing1264.8 Program Example of External Bus Operation127CHAPTER 5 I/O Port1315.1 Overview of I/O Port1325.2 Port 01335.3 Port 11355.4 Port 2, 31375.5 Port 51395.6 Port 6, 71415.7 Port 4, 8, 91455.8 Port A, B1495.9 Port C, D151CHAPTER 6 FG Input1556.1 Overview of FG Input1566.2 Capstan Input1576.3 Drum Input1626.4 Reel Input166CHAPTER 7 FRC Capture1717.1 Overview of FRC Capture1727.2 Register of FRC Capture1747.3 Operation of FRC Capture179CHAPTER 8 Programmable Pulse Generator (PPG0, 1)1818.1 Overview of Programmable Pulse Generator (PPG0, 1)1828.2 Register of Programmable Pulse Generator (PPG0, 1)1858.3 PPG Data RAM1878.4 Configuration of Frame Data1888.5 Operation of PPG189CHAPTER 9 Real Timing Generator (RTG)1919.1 Overview of Real Timing Generator (RTG)1929.2 Register of Real Timing Generator (RTG)1959.3 Operation of Real Timing Generator (RTG)197CHAPTER 10 Timer19910.1 Overview of Timer20010.2 Overview of 16-bit Timer (Timer 0 to 4)20210.3 Register of 16-bit Timer (Timer 0 to 4)20410.4 Operation of 16-bit Timer (Timer 0 to 4)20710.5 Overview of 8-/16-bit Timer/Counter20910.6 Register of 8-/16-bit Timer/Counter21110.7 Operation of 8-/16-bit Timer/Counter215CHAPTER 11 12-bit PWM21711.1 Overview of 12-bit PWM21811.2 Register of 12-bit PWM22011.3 Operation of 12-bit PWM222CHAPTER 12 8-bit Pulse Width Counter22512.1 Overview of 8-bit Pulse Width Counter22612.2 Register of 8-bit Pulse Width Counter22712.3 Operation of 8-bit Pulse Width Counter229CHAPTER 13 External Interrupt23113.1 Overview of External Interrupt23213.2 External Interrupt 1 (Key Input Circuit)23313.3 External Interrupt (INT0 to 2)235CHAPTER 14 Delayed Interrupt Module23914.1 Overview of Delayed Interrupt Module24014.2 Delayed Interrupt Control Register (DICR)24114.3 Operation of Delayed Interrupt Module242CHAPTER 15 Interrupt Controller24315.1 Overview of Interrupt Controller24415.2 Interrupt Control Register (ICRxx)24615.3 Operation of Interrupt Controller247CHAPTER 16 10-bit A/D Converter25116.1 Overview of 10-bit A/D Converter25216.2 Register of 10-bit A/D Converter25316.3 Operation of 10-bit A/D Converter25916.4 State Transition of 10-bit A/D Converter261CHAPTER 17 Serial I/O26317.1 Overview of Serial I/O26417.2 Register of Serial I/O26617.3 Serial Data RAM27017.4 Operation of Serial I/O271CHAPTER 18 10-bit General-purpose Prescaler27518.1 Overview of 10-bit General-purpose Prescaler27618.2 Register of 10-bit General-purpose Prescaler27718.3 Operation of 10-bit General-purpose Prescaler279CHAPTER 19 Bit Search Module28119.1 Overview of Bit Search Module28219.2 Register of Bit Search Module28319.3 Operation of Bit Search Module285CHAPTER 20 Wait Controller28920.1 Outline of Wait Control Section29020.2 Wait Control Register (WAITC)291CHAPTER 21 Flash Memory29321.1 Overview of Flash Memory29421.2 Flash Memory Status Register (FSTR)29821.3 Operation of Flash Memory30021.4 Flash Memory Auto Algorithm (Embedded Algorithm TM)30221.5 Auto Algorithm Execute State306Appendix311Appendix A I/O Map312Appendix B Interrupt vector320Appendix C Measurement accuracy of peripheral circuit322Appendix D Restrictions for Using MB91191/MB91192 series323Appendix E Instruction List324E.1 Instruction list of FR series328Numerics341A341B341C341D342E342F342G342H342I342K343L343M343N343O343P343R344S344T344U345V345W345Размер: 2,4 МБСтраницы: 348Язык: EnglishПросмотреть
