Справочник Пользователя для Mitsubishi Electronics FX

FX Series Programmable Controlers

5-39

The contents of the source device (S) are written to
the FIFO stack. The position of insertion into the
stack is automatically calculated by the PLC.
The destination device (D) is the head address of
the FIFO stack. The contents of D identify where the
next record will be stored (as an offset from D

+1

).

If the contents of D exceed the value “n-1” (n is the
length of the FIFO stack) then insertion into

the FIFO stack is stopped. The carry flag M8022 is
turned ON to identify this situation.

a) FIFO is an abbreviation for ‘First-In/ First-OUT’.

b) Although n devices are assigned for the FIFO stack, only n

-1 

pieces of information may be

written to that stack. This is because the head address device (D) takes the first available
register to store the information regarding the next data insertion point into the FIFO stack.

c) Before starting to use a FIFO stack ensure that the contents of the head address register

(D) are equal to ‘0’ (zero).

d) This instruction should be used in conjunction with SFRD FNC 39. The n parameter 

in both

instructions should be equal.

SFWR
FNC 38
(

Shift 

register

write)

This instruction
creates and builds
a FIFO stack n
devices long -must
be used with
SFRD FNC 39

K, H,
KnX, KnY, 
KnM,KnS,
T, C, D, V, Z

KnY, KnM,
KnS,
T, C, D,

K, H,

Note:
2

≤ 

n

≤ 

512

SFWR,
SFWRP:
7 steps

FX

0(S)

FX

0N

FX FX

(2C)

FX

2N(C)

FX

(2C)

FX

FX

2N(C)

FX

0N

FX

0(s)

PULSE-P

FX

(2C)

FX

FX

2N(C)

FX

0N

FX

0(s)

16 BIT OPERATION

FX

FX

0N

FX

0(s)

FX

(2C)

FX

2N(C)

32 BIT OPERATION

FLAGS Carry M8022

X0

SFWR 

D 1

K 10

[ S ]

[ D ]

D 0

[ n ]

D 0

D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1

[ S ]

= 10

(3)

(2)

(1)

[n]