Справочник Пользователя для Mitsubishi Electronics FX

Скачать
Страница из 382
FX Series Programmable Controlers
Applied Instructions 5
5-56
b) If more than one high speed counter function is used for a single counter the selected flag
devices (D) should be kept within 1 group of 8 devices, i.e. Y0-7, M10-17.
c) All high speed counter functions use an interrupt process, hence, all destination devices (D)
are updated immediately.
5.6.5
HSCR (FNC 54)
Operation:
The HSCR, compares the current value of the
selected high  speed counter (S
2
) aga inst   a
selected value (S
1
). When the counters current
value changes to a value equal to S
1
, the device
specified as the destination (D) is reset. In the example above, Y10 would be reset only when
C255’s value stepped from 199 to 200 or from 201 to 200. If the current value of C255 was
forced to equal 200 by test techniques, output Y10 would NOT reset. 
For further, general points, about using high speed counter functions, please see the
subsection ‘Points to note’ under the HSCS (FNC 53). Relevant points are; a, b, and c.
Please also reference the note about the number of high speed instructions allowable.
Mnemonic
Function 
Operands
Program steps
S
1
S
2
D
HSCR
FNC 54
(High speed
counter
reset)
Resets the
selected output
when the
specified high
speed counter
equals the test
value
K, H,
KnX, KnY, 
KnM, KnS,
T, C, D, V, Z
C
Note:
C = C235 to
C255, or
available high
speed
counters
Y, M, S
C
Note:
If C, use same
counter as S
2
DHSCR:
13 steps
Use of interrupt pointers
FX
(2C) 
and FX
2N 
MPUs can use interrupt pointers I010 through I060 (6 points) as destination
devices (D). This enables interrupt routines to be triggered directly when the value of the
specified high speed counter reaches the value in the HSCS instruction.
Note:
FX
0
,FX
0N 
users - Max. 4 simultaneously active HSCS/R instructions. FX users Max. 6
simultaneously active HSCS/R and HSZ instructions. Please remember that the use of high
speed counter functions has a direct impact on the maximum allowable counting speed! See
page 4-22 for further details.
FX
0(S)
FX
0N
FX FX
(2C)
FX
2N(C)
FX
0(S)
FX
0N
FX FX
(2C)
FX
2N(C)
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
PULSE-P
FX
(2C)
FX
FX
2N(C)
FX
0N
FX
0(s)
16 BIT OPERATION
FX
FX
0N
FX
0(s)
FX
(2C)
FX
2N(C)
32 BIT OPERATION
M8000
C255 Y10
[ S1 ] [ S2 ]
K200
[ D ]
DHSCR