Справочник Пользователя для Mitsubishi Electronics FX

FX Series Programmable Controlers

5-54

This instruction allows a selection of 8 consecutive
input devices (head address S) to be used multiple
(n) times, i.e. each physical input has more than
one, separate and quite different (D

1

) signal being

processed. The result is stored in a matrix-table (head address D

2

). 

a) The MTR instruction involves high speed input/output switching. For this reason this

instruction is only recommended for use with transistor output modules.

b) For the MTR instruction to operate correctly, it must be driven continuously. It is

recommended that special auxiliary relay M8000, the PLC RUN status flag, is used. After
the completion of the first full reading of the matrix, operation complete flag M8029 is turned
ON. This flag is automatically reset when the MTR instruction is turned OFF.

c) Each set of 8 input signals are grouped into a ‘bank’ (there are n number of banks).

d) Each bank is triggered/selected by a dedicated output (head address D

1

). This means the

quantity of outputs from D

1

, used to achieve the matrix are equal to the number of banks n.

As there are now additional inputs entering the PLC these will each have a status which
needs recording. This is stored in a matrix-table. The matrix-table starts at the head address
D

2

. The matrix construction mimics the same 8 signal by n bank configuration. Hence, when

a certain input in a selected bank is read, its status is stored in an equivalent position within
the result matrix-table.

e) The matrix instruction operates on an interrupt format, processing each bank of inputs

every 20msec. This time is based on the selected input filters being set at 10msec. This
wouldresultinan8bankmatrix, i.e. 64inputs(8inputs´8banks) beingreadin160msec.

MTR
FNC 52
(Input
matrix)

Multiplexes a
bank of inputs
into a number of
sets of devices.
Can only be used
ONCE

X

Y

Y, M, S

K, H,

Note:
n=2 to 8

MTR: 9 steps

Note:
These operands should always be 
a multiple of 10, i.e. 00, 10, 20, 30 
etc.

FX

0(S)

FX

0N

FX FX

(2C)

FX

2N(C)

FX

(2C)

FX

FX

2N(C)

FX

0N

FX

0(s)

PULSE-P

FX

(2C)

FX

FX

2N(C)

FX

0N

FX

0(s)

16 BIT OPERATION

FX

FX

0N

FX

0(s)

FX

(2C)

FX

2N(C)

32 BIT OPERATION

FLAGS

Operation

Complete M8029

M8000

M 30

K 3

[ S ]

[ D2 ]

Y 20

[ n ]

X 10

MTR

[ D1 ]

If high speed inputs (ex. X0) is specified for operand S, the reading time of each bank

becomes only 10msec, i.e. a halving of the

reading speed. However, additional pull down
resistors are required on the drive outputs to
ensure the high speed reading does not detect
any residual currents from the last operation.
These should be placed in parallel to the input
bank and should be of a value of approximately
3.3k

Ω

, 0.5W. For easier use, high speed inputs

should not be specified at S.

Y42 Y43 Y44 Y45 Y46 Y47

+V Y40 Y41

X0 X1 X2 X3 X4 X5 X6 X7

24V 0V S/S

Matrix device

Pull down
resistors