Справочник Пользователя для Motorola MC68HC908MR16
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
270
Serial Peripheral Interface Module (SPI)
MOTOROLA
Serial Peripheral Interface Module (SPI)
13.13.1 SPI Control Register
The SPI control register (SPCR):
•
Enables SPI module interrupt requests
•
Selects CPU interrupt requests or DMA service requests
•
Configures the SPI module as master or slave
•
Selects serial clock polarity and phase
•
Configures the SPSCK, MOSI, and MISO pins as open-drain
outputs
outputs
•
Enables the SPI module
SPRIE — SPI Receiver Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
SPRF bit. The SPRF bit is set when a byte transfers from the shift
register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
0 = SPRF CPU interrupt requests disabled
SPMSTR — SPI Master Bit
This read/write bit selects master mode operation or slave mode
operation. Reset sets the SPMSTR bit.
operation. Reset sets the SPMSTR bit.
1 = Master mode
0 = Slave mode
0 = Slave mode
Address: $0044
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPRIE
R
SPMSTR
CPOL
CPHA
SPWOM
SPE
SPTIE
Write:
Reset:
0
0
1
0
1
0
0
0
R
= Reserved
Figure 13-13. SPI Control Register (SPCR)