Справочник Пользователя для Motorola MC68HC908MR16
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
272
Serial Peripheral Interface Module (SPI)
MOTOROLA
Serial Peripheral Interface Module (SPI)
SPTIE— SPI Transmit Interrupt Enable Bit
This read/write bit enables CPU interrupt requests generated by the
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
SPTE bit. SPTE is set when a byte transfers from the transmit data
register to the shift register. Reset clears the SPTIE bit.
1 = SPTE CPU interrupt requests enabled
0 = SPTE CPU interrupt requests disabled
0 = SPTE CPU interrupt requests disabled
13.13.2 SPI Status and Control Register
The SPI status and control register (SPSCR) contains flags to signal
these conditions:
these conditions:
•
Receive data register full
•
Failure to clear SPRF bit before next byte is received (overflow
error)
error)
•
Inconsistent logic level on SS pin (mode fault error)
•
Transmit data register empty
The SPI status and control register also contains bits that perform these
functions:
functions:
•
Enable error interrupts
•
Enable mode fault error detection
•
Select master SPI baud rate
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
the shift register to the receive data register. SPRF generates a CPU
interrupt request if the SPRIE bit in the SPI control register is set also.
Address: $0045
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SPRF
ERRIE
OVRF
MODF
SPTE
MODFEN
SPR1
SPR0
Write:
R
R
R
R
Reset:
0
0
0
0
1
0
0
0
R
= Reserved
Figure 13-14. SPI Status and Control Register (SPSCR)