Справочник Пользователя для Motorola MC68HC908MR16
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MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
336
Low-Voltage Inhibit (LVI)
MOTOROLA
Low-Voltage Inhibit (LVI)
18.4 Functional Description
shows the structure of the LVI module. The LVI is enabled
out of reset. The LVI module contains a bandgap reference circuit and
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V
comparator. The LVI power bit, LVIPWR, enables the LVI to monitor V
DD
voltage. The LVI reset bit, LVIRST, enables the LVI module to generate
a reset when V
a reset when V
DD
falls below a voltage, V
LVRX
, and remains at or below
that level for nine or more consecutive CGMXCLK. V
LVRX
and V
LVHX
are
).
LVIPWR and LVIRST are in the configuration register (CONFIG). See
Once an LVI reset occurs, the MCU remains in reset until V
DD
rises
above a voltage, V
LVRX
+ V
LVHX
. V
DD
must be above V
LVRX
+ V
LVHX
for
. The output of the comparator controls
the state of the LVIOUT flag in the LVI status register (LVISCR).
An LVI reset also drives the RST pin low to provide low-voltage
protection to external peripheral devices. See
protection to external peripheral devices. See
Figure 18-1. LVI Module Block Diagram
LOW V
DD
LVIRST
V
DD
> LVItrip = 0
V
DD
< LVItrip = 1
LVIOUT
LVIPWR
DETECTOR
V
DD
LVI RESET
FROM CONFIG
FROM CONFIG
V
DD
DIGITAL FILTER
CPU CLOCK
ANLGTRIP
TRPSEL
FROM LVISCR