Справочник Пользователя для Motorola MC68HC908MR16
Low-Voltage Inhibit (LVI)
Functional Description
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
Advance Information
MOTOROLA
Low-Voltage Inhibit (LVI)
337
18.4.1 Polled LVI Operation
In applications that can operate at V
DD
levels below V
LVRX
, software can
monitor V
DD
by polling the LVIOUT bit. In the configuration register, the
LVIPWR bit must be at logic 1 to enable the LVI module, and the LVIRST
bit must be at logic 0 to disable LVI resets. See
bit must be at logic 0 to disable LVI resets. See
. TRPSEL in the LVISCR selects
V
LVRX
.
18.4.2 Forced Reset Operation
In applications that require V
DD
to remain above V
LVRX
, enabling LVI
resets allows the LVI module to reset the MCU when V
DD
falls to the
V
LVRX
level and remains at or below that level for nine or more
consecutive CPU cycles. In the CONFIG register, the LVIPWR and
LVIRST bits must be at logic 1 to enable the LVI module and to enable
LVI resets. TRPSEL in the LVISCR selects V
LVIRST bits must be at logic 1 to enable the LVI module and to enable
LVI resets. TRPSEL in the LVISCR selects V
LVRX
.
18.4.3 False Reset Protection
The V
DD
pin level is digitally filtered to reduce false resets due to power
supply noise. In order for the LVI module to reset the MCU, V
DD
must
remain at or below V
LVRX
for nine or more consecutive CPU cycles. V
DD
must be above V
LVRX
+ V
LVHX
for only one CPU cycle to bring the MCU
out of reset. TRPSEL in the LVISCR selects V
LVRX
+ V
LVHX
.
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$FE0F
LVI Status and Control
Register (LVISCR)
Read: LVIOUT
0
TRPSEL
0
0
0
0
0
Write:
R
R
R
R
R
R
R
Reset:
0
0
0
0
0
0
0
0
R
= Reserved
Figure 18-2. LVI I/O Register Summary