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Low-Voltage Inhibit (LVI)

LVI Interrupts

MC68HC908MR16/MC68HC908MR32 — Rev. 4.0

Advance Information

MOTOROLA

Low-Voltage Inhibit (LVI)

339

TRPSEL — LVI Trip Select Bit

This bit selects the LVI trip point. Reset clears this bit.

1 = 5 percent tolerance. The trip point and recovery point are

determined by V

LVR1

and V

LVH1

, respectively.

0 = 10 percent tolerance. The trip point and recovery point are

determined by V

LVR2

and V

LVH2

, respectively.

NOTE:

If LVIRST and LVIPWR are at logic 0, note that when changing the
tolerence, LVI reset will be generated if the supply voltage is below the
trip point.

18.6 LVI Interrupts

The LVI module does not generate interrupt requests.

18.7 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby
mode.

With the LVIPWR bit in the configuration register programmed to logic 1,
the LVI module is active after a WAIT instruction.

With the LVIRST bit in the configuration register programmed to logic 1,
the LVI module can generate a reset and bring the MCU out of wait
mode.

Table 18-1. LVIOUT Bit Indication

LVIOUT

At Level:

For Number of

CGMXCLK Cycles:

> V

LVRX

+ V

LVHX

Any

LVRX

< 32 CGMXCLK cycles

LVRX

Between 32 & 40 CGMXCLK cycles

0 or 1

LVRX

> 40 CGMXCLK cycles

LVRX

+ V

LVHX

Any

value