Справочник Пользователя для Motorola MC68HC908MR16
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
344
Analog-to-Digital Converter (ADC)
MOTOROLA
Analog-to-Digital Converter (ADC)
19.4.2 Voltage Conversion
When the input voltage to the ADC equals V
REFH
, the ADC converts the
signal to $3FF (full scale). If the input voltage equals V
REFL
,
the ADC
converts it to $000. Input voltages between V
REFH
and V
REFL
are
straight-line linear conversions. All other input voltages will result in
$3FF if greater than V
$3FF if greater than V
REFH
and $000 if less than V
REFL
.
NOTE:
Input voltage should not exceed the analog supply voltages. See
.
19.4.3 Conversion Time
Conversion starts after a write to the ADSCR. A conversion is between
16 and 17 ADC clock cycles, therefore:
16 and 17 ADC clock cycles, therefore:
The ADC conversion time is determined by the clock source chosen and
the divide ratio selected. The clock source is either the bus clock or
CGMXCLK and is selectable by ADICLK located in the ADC clock
register. For example, if CGMXCLK is 4 MHz and is selected as the ADC
input clock source, the ADC input clock divide-by-4 prescale is selected
and the CPU bus frequency is 8 MHz:
the divide ratio selected. The clock source is either the bus clock or
CGMXCLK and is selectable by ADICLK located in the ADC clock
register. For example, if CGMXCLK is 4 MHz and is selected as the ADC
input clock source, the ADC input clock divide-by-4 prescale is selected
and the CPU bus frequency is 8 MHz:
NOTE:
The ADC frequency must be between f
ADIC
minimum and f
ADIC
maximum to meet A/D specifications. See
Since an ADC cycle may be comprised of several bus cycles (eight, 136
minus 128, in the previous example) and the start of a conversion is
initiated by a bus cycle write to the ADSCR, from zero to eight additional
bus cycles may occur before the start of the initial ADC cycle. This
results in a fractional ADC cycle and is represented as the 17th cycle.
minus 128, in the previous example) and the start of a conversion is
initiated by a bus cycle write to the ADSCR, from zero to eight additional
bus cycles may occur before the start of the initial ADC cycle. This
results in a fractional ADC cycle and is represented as the 17th cycle.
16 to17 ADC Cycles
Conversion time =
ADC Frequency
Number of Bus Cycles = Conversion Time x CPU Bus Frequency
16 to 17 ADC Cycles
Conversion Time =
4 MHz/4
Number of bus cycles = 16
µ
s x 8 MHz = 128 to 136 cycles
= 16 to 17
µ
s