Справочник Пользователя для Motorola MC68HC908MR16
System Integration Module (SIM)
Reset and System Initialization
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
Advance Information
MOTOROLA
System Integration Module (SIM)
95
7.4.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK
cycles to allow resetting of external peripherals. The internal reset
signal (IRST) continues to be asserted for an additional 32 cycles (see
cycles to allow resetting of external peripherals. The internal reset
signal (IRST) continues to be asserted for an additional 32 cycles (see
). An internal reset can be caused by an illegal address, illegal
opcode, COP timeout, LVI, or POR. (See
Figure 7-4. Sources of Internal Reset
NOTE:
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST, as shown in
during which the SIM forces the RST pin low. The internal reset signal
then follows the sequence from the falling edge of RST, as shown in
.
Figure 7-5. Internal Reset Timing
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals
and other chips within a system built around the MCU.
and other chips within a system built around the MCU.
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
POR
INTERNAL RESET
IRST
RST
RST PULLED LOW BY MCU
IAB
32 CYCLES
32 CYCLES
VECTOR HIGH
CGMXCLK