Справочник Пользователя для Motorola MC68HC908MR16
Advance Information
MC68HC908MR16/MC68HC908MR32 — Rev. 4.0
98
System Integration Module (SIM)
MOTOROLA
System Integration Module (SIM)
7.4.2.5 Forced Monitor Mode Entry Reset (MENRST)
The MENRST module monitors the reset vector fetches and will assert
an internal reset if it detects that the reset vectors are erased ($FF).
When the MCU comes out of reset, it is forced into monitor mode.
an internal reset if it detects that the reset vectors are erased ($FF).
When the MCU comes out of reset, it is forced into monitor mode.
7.4.2.6 Low-Voltage Inhibit (LVI) Reset
The low-voltage inhibit (LVI) module asserts its output to the SIM when
the V
the V
DD
voltage falls to the V
LVRX
voltage and remains at or below that
level for at least nine consecutive CPU cycles (see
). The LVI bit in the SIM reset
status register (SRSR) is set, and the external reset pin (RST) is held low
while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four
CGMXCLK cycles later, the CPU is released from reset to allow the reset
vector sequence to occur. The SIM actively pulls down the RST pin for
all internal reset sources.
while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four
CGMXCLK cycles later, the CPU is released from reset to allow the reset
vector sequence to occur. The SIM actively pulls down the RST pin for
all internal reset sources.
7.5 SIM Counter
The SIM counter is used by the power-on reset (POR) module to allow
the oscillator time to stabilize before enabling the internal bus (IBUS)
clocks. The SIM counter also serves as a prescaler for the computer
operating properly (COP) module. The SIM counter overflow supplies
the clock for the COP module. The SIM counter is 13 bits long and is
clocked by the falling edge of CGMXCLK.
the oscillator time to stabilize before enabling the internal bus (IBUS)
clocks. The SIM counter also serves as a prescaler for the computer
operating properly (COP) module. The SIM counter overflow supplies
the clock for the COP module. The SIM counter is 13 bits long and is
clocked by the falling edge of CGMXCLK.
7.5.1 SIM Counter During Power-On Reset
The power-on reset (POR) module detects power applied to the MCU.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation (CGM) module to drive the
bus clock state machine.
At power-on, the POR circuit asserts the signal PORRST. Once the SIM
is initialized, it enables the clock generation (CGM) module to drive the
bus clock state machine.
7.5.2 SIM Counter and Reset States
External reset has no effect on the SIM counter. The SIM counter is
free-running after all reset states. For counter control and internal reset
recovery sequences, see
free-running after all reset states. For counter control and internal reset
recovery sequences, see