Справочник ПользователяСодержание1. Features12. Logic Block Diagram13. Applications24. Introduction25. Conventions26. Pinouts36.1 Pin Assignments47. Register Summary68. CPU Architecture89. CPU Registers89.1 Flags Register89.1.1 Accumulator Register99.1.2 Index Register99.1.3 Stack Pointer Register99.1.4 CPU Program Counter High Register99.1.5 CPU Program Counter Low Register99.2 Addressing Modes109.2.1 Source Immediate109.2.2 Source Direct109.2.3 Source Indexed109.2.4 Destination Direct109.2.5 Destination Indexed119.2.6 Destination Direct Source Immediate119.2.7 Destination Indexed Source Immediate119.2.8 Destination Direct Source Direct119.2.9 Source Indirect Post Increment129.2.10 Destination Indirect Post Increment1210. Instruction Set Summary1211. Memory Organization1411.1 Flash Program Memory Organization1411.2 Data Memory Organization1511.3 Flash1511.3.1 Flash Programming and Security1511.3.2 In-System Programming1511.4 SROM1511.4.1 Return Codes1611.5 SROM Function Descriptions1611.5.1 SWBootReset Function1611.5.2 ReadBlock Function1611.5.3 WriteBlock Function1711.5.4 EraseBlock Function1711.5.5 ProtectBlock Function1711.5.6 EraseAll Function1811.5.7 TableRead Function1811.6 SROM Table Read Description1911.6.1 Checksum Function2012. Clocking2112.1 Trim Values for the IOSCTR Register2112.2 Clock Architecture Description2212.2.1 CPU Clock2212.2.2 Interval Timer Clock (ITMRCLK)2512.2.3 Timer Capture Clock (TCAPCLK)2612.2.4 Internal Clock Trim2812.2.5 External Clock Trim2812.2.6 LPOSC Trim2912.3 CPU Clock During Sleep Mode2913. Reset3013.1 Power On Reset3113.2 Watchdog Timer Reset3114. Sleep Mode3114.1 Sleep Sequence3214.1.1 Low Power in Sleep Mode3214.2 Wakeup Sequence3315. Low Voltage Detect Control3415.1 POR Compare State3515.2 ECO Trim Register3516. General Purpose IO Ports3616.1 Port Data Registers3616.1.1 P0 Data3616.1.2 P1 Data3616.1.3 P2 Data3716.1.4 P3 Data3716.1.5 P4 Data3716.2 GPIO Port Configuration3716.2.1 Int Enable3716.2.2 Int Act Low3716.2.3 TTL Thresh3716.2.4 High Sink3816.2.5 Open Drain3816.2.6 Pull Up Enable3816.2.7 Output Enable3816.2.8 SPI Use3816.2.9 P0.0/CLKIN Configuration3816.2.10 P0.1/CLKOUT Configuration3916.2.11 P0.2/INT0-P0.4/INT2 Configuration3916.2.12 P0.5/TIO0-P0.6/TIO1 Configuration4016.2.13 P0.7 Configuration4016.2.14 P1.0 Configuration4016.2.15 P1.1 Configuration4116.2.16 P1.2 Configuration4116.2.17 P1.3 Configuration (SSEL)4116.2.18 P1.4-P1.6 Configuration (SCLK, SMOSI, SMISO)4216.2.19 P1.7 Configuration4216.2.20 P2 Configuration4216.2.21 P3 Configuration4316.2.22 P4 Configuration4317. Serial Peripheral Interface (SPI)4417.1 SPI Data Register4517.2 SPI Configure Register4517.3 SPI Interface Pins4718. Timer Registers4718.1 Registers4718.1.1 Free Running Counter4718.1.2 Time Capture4818.1.3 Programmable Interval Timer5019. Interrupt Controller5419.1 Architectural Description5419.2 Interrupt Processing5519.3 Interrupt Latency5519.4 Interrupt Registers5519.4.1 Interrupt Clear Register5519.4.2 Interrupt Mask Registers5619.4.3 Interrupt Vector Clear Register5820. Absolute Maximum Ratings5920.1 DC Characteristics5920.2 AC Characteristics6021. Ordering Information6322. Package Handling6323. Package Diagrams6424. Document History Page67Sales, Solutions, and Legal Information68Worldwide Sales and Design Support68Products68PSoC Solutions68Размер: 1,4 МБСтраницы: 68Язык: EnglishПросмотреть