Инструкции для Cypress CYS25G0101DX-ATC

Содержание

• 1. Introduction

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• 2. Features

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• 3. Kit Contents

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• 4. Functional Description

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• 5. Diagnostic Modes

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• 5.1 Diagnostic Loopback Mode

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• 5.2 Line Loopback

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• 5.3 Analog Line Loopback

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• 5.4 “Parallel Line Loopback” (TEST0) Mode

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• 5.4.1 Test the Internal RX CDR PLL Only

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• 5.4.2 Test the Internal RX CDR PLL and TX PLL

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• 6. Testing Hookup

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• 6.1 Set-up for BERT Test

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• 6.2 Set-up for Eye Diagram Test

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• 6.3 SONET Jitter Transfer and Jitter Tolerance Test

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• 6.4 Set-up for Testing the TX PLL in Parallel Line Loopback Mode

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• 7. Eye Diagram Testing Result

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• 8. Jitter Transfer Testing Result

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• 9. Jitter Tolerance Testing Result

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• 10. Schematic Diagram, PCB Layout and BOM (Bill of Material)

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• Appendix A: Schematic Diagrams of the CYS25G0101DX Evaluation Board

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• Appendix B: PCB Layout Diagrams of the CYS25G0101DX Evaluation Board

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• Appendix C: CYS25G0101DX Evaluation Board LVPECL BOM (Bill of Material)

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• Appendix D: CYS25G0101DX Evaluation Board HSTL BOM (Bill of Material)

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• Figure 1. The Block Diagram of the CYS25G0101DX

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• Figure 2. The CYS25G0101DX Evaluation Board

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• Figure 3. The Jumper Orientations of the CYS25G0101DX

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• Figure 4. Diagnostic Loopback Mode Data Path

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• Figure 5. Line Loopback Mode Data Path

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• Figure 6. Analog Line Loopback Mode Data Path

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• Figure 7. Parallel Loopback (TEST0) Mode Data Path

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• Figure 8. Equipment Set-up for BERT Test

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• Figure 9. Equipment Set-up For Eye Diagram Test

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• Figure 10. Equipment Set-up For Jitter Test

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• Figure 11. Equipment Set-up For Testing the TX PLL in Parallel Line Loopback Mode

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• Figure 12. CYS25G0101DX Evaluation Board Eye Diagram

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• Figure 13. CYS25G0101DX Evaluation Board GR-253 Jitter Transfer Testing Result

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• Figure 14. CYS25G0101DX Evaluation Board G958 Jitter Transfer Testing Result

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• Figure 15. CYS25G0101DX Evaluation Board GR-253 JitterTolerance Testing Result

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• Figure 16. CYS25G0101DX Evaluation Board G825 Jitter Tolerance Testing Result

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• Figure 17. Top Level of CYS25G0101DX Evaluation Board Schematic Diagram

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• Figure 18. Parallel Output Block Schematic Diagram

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• Figure 19. Parallel Input Block Schematic Diagram

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• Figure 20. Signals Block Schematic Diagram

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• Figure 21. Power Supply Block Schematic Diagram

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• Figure 22. Control Block Schematic Diagram

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• Figure 23. Reference Clock Block Schematic Diagram

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• Figure 24. CYS25G0101DX Evaluation Board PCB Mechanical Drawing

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• Figure 25. CYS25G0101DX Evaluation Board PCB Top Layer Silk Screen

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• Figure 26. CYS25G0101DX Evaluation Board PCB Top Layer Layout

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• Figure 27. CYS25G0101DX Evaluation Board PCB Top Layer Solder Mask

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• Figure 28. CYS25G0101DX Evaluation Board PCB Power Plane Layout

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• Figure 29. CYS25G0101DX Evaluation Board PCB Ground Plane Layout

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• Figure 30. CYS25G0101DX Evaluation Board PCB Bottom Silk Screen

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• Figure 31. CYS25G0101DX Evaluation Board PCB Bottom Layer Layout

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• Figure 32. CYS25G0101DX Evaluation Board PCB Bottom Solder Mask

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• Table 1. Functional Description of the Connectors

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• Table 2. Pin Assignment of J1 Header and Description of J10 Header

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• Table 3. Pin Assignment of J2 Header and Description of J9 Header

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• Table 4. Functional Description of DIP Switch 1 (SW1)

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• Table 5. Functional Description of J4 Connector

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• Table 6. Description of LED Indicators

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• Table 7. Operation Specification of CYS25G0101DX Evaluation Board

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• Table 8. CYS25G0101DX Evaluation Board LVPECL BOM - Page 1 of 4

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• Table 9. CYS25G0101DX Evaluation Board LVPECL BOM - Page 2 of 4

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• Table 10. CYS25G0101DX Evaluation Board LVPECL BOM - Page 3 of 4

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• Table 11. CYS25G0101DX Evaluation Board LVPECL BOM - Page 4 of 4

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• Table 12. CYS25G0101DX Evaluation Board HSTL BOM - Page 1 of 4

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• Table 13. CYS25G0101DX Evaluation Board HSTL BOM - Page 2 of 4

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• Table 14. CYS25G0101DX Evaluation Board HSTL BOM - Page 3 of 4

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• Table 15. CYS25G0101DX Evaluation Board HSTL BOM - Page 4 of 4

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