Инструкции для Intel N455

Содержание

• Intel® Atom™ Processor N400 Series

  1
• Revision History

  7
• 1 Introduction

  8
  • 1.1 Processor Features

    8
  • 1.2 Interfaces

    9
    • 1.2.1 System Memory Support

      9
    • 1.2.2 Direct Media Interface Features

      9
    • 1.2.3 Integrated Graphics Controller

      10
  • 1.3 Clocking

    10
  • 1.4 Power Management Support

    11
  • 1.5 Package

    11
  • 1.6 Terminology

    11
  • 1.7 References

    12
  • 1.8 System Block Diagram

    13
• 2 Signal Description

  14
  • 2.1 Processor Legacy Signals

    15
  • 2.2 System Memory Interface

    18
  • 2.3 Reset and Miscellaneous Signals

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  • 2.4 DMI - Direct Media Interface

    20
  • 2.5 PLL Signals

    21
  • 2.6 Analog Display Signals

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  • 2.7 LVDS Signals

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  • 2.8 TAP Signals

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  • 2.9 Error and Thermal Protection

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  • 2.10 Processor Core Power Signals

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  • 2.11 Graphics, DMI and Memory Core Power Signals

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  • 2.12 Ground

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• 3 Functional Description

  25
  • 3.1 Integrated Memory Controller

    25
    • 3.1.1 System Memory Organization Modes

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    • 3.1.2 System Memory Technology Supported

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    • 3.1.3 Rules for populating SO-DIMM slots

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    • 3.1.4 Intel® Fast Memory Access (Intel® FMA) Technology Enhancements

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    • 3.1.5 DRAM Clock Generation

      27
  • 3.2 Integrated Graphics Controller

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    • 3.2.1 3D Graphics Pipeline

      28
    • 3.2.2 Video Engine

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    • 3.2.3 2D Engine

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    • 3.2.4 Display Pipes

      31
    • 3.2.5 Display Ports

      31
    • 3.2.6 VESA/VGA Mode

      35
    • 3.2.7 Multiple Display Configurations

      35
  • 3.3 Thermal Sensor

    35
    • 3.3.1 PCI Device 0, Function 0

      35
  • 3.4 Power Management

    36
  • 3.5 Intel® Hyper-Threading Technology

    36
• 4 Electrical Specifications

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  • 4.1 Power and Ground Balls

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  • 4.2 Decoupling Guidelines

    37
    • 4.2.1 Voltage Rail Decoupling

      37
  • 4.3 Processor Clocking

    37
    • 4.3.1 PLL Power Supply

      38
  • 4.4 Voltage Identification (VID)

    38
  • 4.5 Catastrophic Thermal Protection

    40
  • 4.6 Reserved or Unused Signals

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  • 4.7 Signal Groups

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  • 4.8 Test Access Port (TAP) Connection

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  • 4.9 Absolute Maximum and Minimum Ratings

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  • 4.10 DC Specifications

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    • 4.10.1 Voltage and Current Specifications

      42
    • 4.10.2 Interface DC Specifications

      46
• 5 Power Management

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  • 5.1 ACPI States Supported

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    • 5.1.1 System States

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    • 5.1.2 Processor Idle States

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    • 5.1.3 Integrated Graphics Display States

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    • 5.1.4 Integrated Memory Controller States

      53
    • 5.1.5 DMI States

      53
    • 5.1.6 Interface State Combinations

      53
  • 5.2 Processor Core Power Management

    54
    • 5.2.1 Enhanced Intel® SpeedStep Technology

      54
    • 5.2.2 Dynamic Cache Sizing

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    • 5.2.3 Low-Power Idle States

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    • 5.2.4 Thread C-states Description

      58
    • 5.2.5 Processor Core/Package C-states Description

      59
  • 5.3 External Thermal Sensor PM_EXTTS1#: Implementation for Fast C4/C4E Exit

    62
• 6 Thermal Specifications and Design Considerations

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  • 6.1 Thermal Specifications

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    • 6.1.1 Thermal Diode

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    • 6.1.2 Intel® Thermal Monitor

      67
    • 6.1.3 Digital Thermal Sensor

      69
    • 6.1.4 Out of Specification Detection

      70
    • 6.1.5 PROCHOT# Signal Pin

      70
• 7 Package Mechanical Specifications and Ball Information

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  • 7.1 Package Mechanical Specifications

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    • 7.1.1 Package Mechanical Drawings

      72
    • 7.1.2 Package Loading Specifications

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  • 7.2 Processor Ballout Assignment

    73