Инструкции для NEC PD78F9488

Содержание

• COVER

  1
• INTRODUCTION

  8
• CHAPTER 1 GENERAL

  26
  • 1.1 Features

    26
  • 1.2 Applications

    26
  • 1.3 Ordering Information

    27
  • 1.4 Pin Configuration (Top View)

    28
  • 1.5 78K/0S Series Lineup

    31
  • 1.6 Block Diagram

    34
  • 1.7 Overview of Functions

    35
• CHAPTER 2 PIN FUNCTIONS

  37
  • 2.1 List of Pin Functions

    37
  • 2.2 Description of Pin Functions

    40
    • 2.2.1 P00 to P07 (Port 0)

      40
    • 2.2.2 P10, P11 (Port 1)

      40
    • 2.2.3 P20 to P25 (Port 2)

      40
    • 2.2.4 P30 to P34 (Port 3)

      41
    • 2.2.5 P50 to P53 (Port 5)

      41
    • 2.2.6 P60 to P67 (Port 6)

      42
    • 2.2.7 P70 to P73 (Port 7)

      42
    • 2.2.8 P80 to P87 (Port 8)

      42
    • 2.2.9 S0 to S27

      42
    • 2.2.10 COM0 to COM3

      42
    • 2.2.11 VLC0 to VLC2

      42
    • 2.2.12 CAPH, CAPL

      42
    • 2.2.13 RESET#

      43
    • 2.2.14 X1, X2

      43
    • 2.2.15 XT1, XT2

      43
    • 2.2.16 AVDD

      43
    • 2.2.17 AVSS

      43
    • 2.2.18 VDD

      43
    • 2.2.19 VSS

      43
    • 2.2.20 VPP (flash memory version only)

      43
    • 2.2.21 IC0 (mask ROM version only)

      44
  • 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins

    45
• CHAPTER 3 CPU ARCHITECTURE

  48
  • 3.1 Memory Space

    48
    • 3.1.1 Internal program memory space

      52
    • 3.1.2 Internal data memory space

      53
    • 3.1.3 Special function register (SFR) area

      53
    • 3.1.4 Data memory addressing

      54
  • 3.2 Processor Registers

    58
    • 3.2.1 Control registers

      58
    • 3.2.2 General-purpose registers

      61
    • 3.2.3 Special function registers (SFRs)

      62
  • 3.3 Instruction Address Addressing

    66
    • 3.3.1 Relative addressing

      66
    • 3.3.2 Immediate addressing

      67
    • 3.3.3 Table indirect addressing

      68
    • 3.3.4 Register addressing

      68
  • 3.4 Operand Address Addressing

    69
    • 3.4.1 Direct addressing

      69
    • 3.4.2 Short direct addressing

      70
    • 3.4.3 Special function register (SFR) addressing

      71
    • 3.4.4 Register addressing

      72
    • 3.4.5 Register indirect addressing

      73
    • 3.4.6 Based addressing

      74
    • 3.4.7 Stack addressing

      74
• CHAPTER 4 PORT FUNCTIONS

  75
  • 4.1 Port Functions

    75
  • 4.2 Port Configuration

    76
    • 4.2.1 Port 0

      77
    • 4.2.2 Port 1

      78
    • 4.2.3 Port 2

      79
    • 4.2.4 Port 3

      84
    • 4.2.5 Port 5

      86
    • 4.2.6 Port 6

      87
    • 4.2.7 Port 7

      89
    • 4.2.8 Port 8

      90
  • 4.3 Registers Controlling Port Function

    91
  • 4.4 Port Function Operation

    94
    • 4.4.1 Writing to I/O port

      94
    • 4.4.2 Reading from I/O port

      94
    • 4.4.3 Arithmetic operation of I/O port

      94
• CHAPTER 5 CLOCK GENERATOR

  95
  • 5.1 Clock Generator Functions

    95
  • 5.2 Clock Generator Configuration

    95
  • 5.3 Registers Controlling Clock Generator

    98
  • 5.4 System Clock Oscillators

    101
    • 5.4.1 Main system clock oscillator

      101
    • 5.4.2 Subsystem clock oscillator

      102
    • 5.4.3 Example of incorrect resonator connection

      103
    • 5.4.4 Divider circuit

      104
    • 5.4.5 When subsystem clock is not used

      104
    • 5.4.6 Subsystem clock (4 multiplication circuit

      104
  • 5.5 Clock Generator Operation

    105
  • 5.6 Changing Setting of System Clock and CPU Clock

    106
    • 5.6.1 Time required for switching between system clock and CPU clock

      106
    • 5.6.2 Switching between system clock and CPU clock

      107
• CHAPTER 6 16-BIT TIMER 20

  108
  • 6.1 16-Bit Timer 20 Functions

    108
  • 6.2 16-Bit Timer 20 Configuration

    108
  • 6.3 Registers Controlling 16-Bit Timer 20

    110
  • 6.4 16-Bit Timer 20 Operation

    113
    • 6.4.1 Operation as timer interrupt

      113
    • 6.4.2 Operation as timer output

      115
    • 6.4.3 Capture operation

      116
    • 6.4.4 16-bit timer counter 20 readout

      117
  • 6.5 Cautions on Using 16-Bit Timer 20

    118
    • 6.5.1 Restrictions when rewriting 16-bit compare register 20

      118
• CHAPTER 7 8-BIT TIMERS 50, 60, AND 61

  120
  • 7.1 Functions of 8-Bit Timers 50, 60, and 61

    120
  • 7.2 Configuration of 8-Bit Timers 50, 60, and 61

    122
  • 7.3 Control Registers for 8-Bit Timers 50, 60, and 61

    128
  • 7.4 Operation of 8-Bit Timers 50, 60, and 61

    134
    • 7.4.1 Operation as 8-bit timer counter

      134
    • 7.4.2 Operation as 16-bit timer counter

      143
    • 7.4.3 Operation as carrier generator

      150
    • 7.4.4 PWM output mode operation (timer 50)

      154
    • 7.4.5 PPG output mode operation (timer 60 and timer 61)

      158
  • 7.5 Cautions on Using 8-Bit Timers 50, 60, and 61

    160
• CHAPTER 8 WATCH TIMER

  161
  • 8.1 Watch Timer Functions

    161
  • 8.2 Configuration of Watch Timer

    162
  • 8.3 Control Registers for Watch Timer

    163
  • 8.4 Watch Timer Operation

    165
    • 8.4.1 Operation as watch timer

      165
    • 8.4.2 Operation as interval timer

      165
• CHAPTER 9 WATCHDOG TIMER

  167
  • 9.1 Watchdog Timer Functions

    167
  • 9.2 Watchdog Timer Configuration

    168
  • 9.3 Watchdog Timer Control Registers

    169
  • 9.4 Watchdog Timer Operation

    171
    • 9.4.1 Operation as watchdog timer

      171
    • 9.4.2 Operation as interval timer

      172
• CHAPTER 10 10-BIT A/D CONVERTER

  173
  • 10.1 10-Bit A/D Converter Functions

    173
  • 10.2 10-Bit A/D Converter Configuration

    173
  • 10.3 10-Bit A/D Converter Control Registers

    176
  • 10.4 10-Bit A/D Converter Operation

    178
    • 10.4.1 Basic operation of 10-bit A/D converter

      178
    • 10.4.2 Input voltage and conversion result

      179
    • 10.4.3 Operation mode of 10-bit A/D converter

      181
  • 10.5 Cautions Related to 10-Bit A/D Converter

    182
• CHAPTER 11 SERIAL INTERFACE 20

  186
  • 11.1 Serial Interface 20 Functions

    186
  • 11.2 Serial Interface 20 Configuration

    186
  • 11.3 Serial Interface 20 Control Registers

    190
  • 11.4 Serial Interface 20 Operation

    197
    • 11.4.1 Operation stop mode

      197
    • 11.4.2 Asynchronous serial interface (UART) mode

      199
    • 11.4.3 3-wire serial I/O mode

      211
• CHAPTER 12 SERIAL INTERFACE 1A0

  216
  • 12.1 Function of Serial Interface 1A0

    216
  • 12.2 Configuration of Serial Interface 1A0

    217
  • 12.3 Control Registers for Serial Interface 1A0

    219
  • 12.4 Serial Interface 1A0 Operation

    224
    • 12.4.1 Operation stop mode

      224
    • 12.4.2 3-wire serial I/O mode

      225
    • 12.4.3 3-wire serial I/O mode with automatic transmit/receive function

      230
• CHAPTER 13 LCD CONTROLLER/DRIVER

  250
  • 13.1 LCD Controller/Driver Functions

    250
  • 13.2 LCD Controller/Driver Configuration

    250
  • 13.3 Registers Controlling LCD Controller/Driver

    253
  • 13.4 Setting LCD Controller/Driver

    257
  • 13.5 LCD Display Data Memory

    257
  • 13.6 Common and Segment Signals

    258
  • 13.7 Display Modes

    260
    • 13.7.1 Three-time-slice display example

      260
    • 13.7.2 Four-time-slice display example

      263
  • 13.8 Supplying LCD Drive Voltages VLC0, VLC1, and VLC2

    266
• CHAPTER 14 MULTIPLIER

  267
  • 14.1 Multiplier Function

    267
  • 14.2 Multiplier Configuration

    267
  • 14.3 Multiplier Control Register

    269
  • 14.4 Multiplier Operation

    270
• CHAPTER 15 REMOTE CONTROLLER RECEIVER (uPD789489, 78F9489 ONLY)

  271
  • 15.1 Remote Controller Receiver Functions

    271
  • 15.2 Remote Controller Receiver Configuration

    271
  • 15.3 Registers to Control Remote Controller Receiver

    277
  • 15.4 Operation of Remote Controller Receiver

    279
    • 15.4.1 Format of type A reception mode

      279
    • 15.4.2 Operation flow of type A reception mode

      279
    • 15.4.3 Timing

      281
    • 15.4.4 Compare register setting

      283
    • 15.4.5 Error interrupt generation timing

      285
    • 15.4.6 Noise elimination

      287
• CHAPTER 16 INTERRUPT FUNCTIONS

  290
  • 16.1 Interrupt Function Types

    290
  • 16.2 Interrupt Sources and Configuration

    290
  • 16.3 Registers Controlling Interrupt Function

    294
  • 16.4 Interrupt Servicing Operation

    301
    • 16.4.1 Non-maskable interrupt request acknowledgment operation

      301
    • 16.4.2 Maskable interrupt request acknowledgment operation

      303
    • 16.4.3 Multiple interrupt servicing

      304
    • 16.4.4 Putting interrupt requests on hold

      306
• CHAPTER 17 STANDBY FUNCTION

  307
  • 17.1 Standby Function and Configuration

    307
    • 17.1.1 Standby function

      307
    • 17.1.2 Register controlling standby function

      308
  • 17.2 Standby Function Operation

    309
    • 17.2.1 HALT mode

      309
    • 17.2.2 STOP mode

      312
• CHAPTER 18 RESET FUNCTION

  315
• CHAPTER 19 FLASH MEMORY VERSION

  319
  • 19.1 Flash Memory Characteristics

    320
    • 19.1.1 Programming environment

      320
    • 19.1.2 Communication mode

      321
    • 19.1.3 On-board pin processing

      324
    • 19.1.4 Connection of adapter for flash writing

      327
  • 19.2 Cautions on uPD78F9488 and 78F9489

    330
• CHAPTER 20 MASK OPTIONS

  331
• CHAPTER 21 INSTRUCTION SET

  332
  • 21.1 Operation

    332
    • 21.1.1 Operand identifiers and description methods

      332
    • 21.1.2 Description of “Operation” column

      333
    • 21.1.3 Description of “Flag” column

      333
  • 21.2 Operation List

    334
  • 21.3 Instructions Listed by Addressing Type

    339
• CHAPTER 22 ELECTRICAL SPECIFICATIONS (uPD789488, 78F9488, 789489, 78F9489)

  342
• CHAPTER 23 CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)

  362
• CHAPTER 24 PACKAGE DRAWINGS

  364
• CHAPTER 25 RECOMMENDED SOLDERING CONDITIONS

  366
• APPENDIX A DEVELOPMENT TOOLS

  369
  • A.1 Software Package

    371
  • A.2 Language Processing Software

    371
  • A.3 Control Software

    372
  • A.4 Flash Memory Writing Tools

    372
  • A.5 Debugging Tools (Hardware)

    373
  • A.6 Debugging Tools (Software)

    374
• APPENDIX B NOTES ON TARGET SYSTEM DESIGN

  375
• APPENDIX C REGISTER INDEX

  379
• APPENDIX D REVISION HISTORY

  385