Инструкции для st--t upsd3212cv

Содержание

• FEATURES SUMMARY

  1
  • Figure 1. Packages

    1
  • Table 1. Device Summary

    2
• SUMMARY DESCRIPTION

  7
  • Figure 2. Block Diagram

    7
  • Figure 3. TQFP52 Connections

    8
  • Figure 4. TQFP80 Connections

    9
  • Table 2. 80-Pin Package Pin Description

    10
• 52-PIN PACKAGE I/O PORT

  12
• ARCHITECTURE OVERVIEW

  13
  • Memory Organization

    13
    • Figure 5. Memory Map and Address Space

      13
  • Registers

    14
    • Figure 6. 8032 MCU Registers

      14
    • Figure 7. Configuration of BA 16-bit Registers

      14
    • Figure 8. Stack Pointer

      14
    • Figure 9. PSW (Program Status Word) Register

      15
  • Program Memory

    15
  • Data memory

    15
  • RAM

    15
  • XRAM-PSD

    15
    • Figure 10. Interrupt Location of Program Memory

      15
  • SFR

    16
    • Table 3. RAM Address

      16
  • Addressing Modes

    16
    • Figure 11. Direct Addressing

      16
    • Figure 12. Indirect Addressing

      16
    • Figure 13. Indexed Addressing

      17
  • Arithmetic Instructions

    17
    • Table 4. Arithmetic Instructions

      18
  • Logical Instructions

    18
    • Table 5. Logical Instructions

      19
  • Data Transfers

    20
    • Table 6. Data Transfer Instructions that Access Internal Data Memory Space

      20
    • Table 7. Shifting a BCD Number Two Digits to the Right (using direct MOVs: 14 bytes)

      21
    • Table 8. Shifting a BCD Number Two Digits to the Right (using direct XCHs: 9 bytes)

      21
    • Table 9. Shifting a BCD Number One Digit to the Right

      21
    • Table 10. Data Transfer Instruction that Access External Data Memory Space

      22
    • Table 11. Lookup Table READ Instruction

      22
  • Boolean Instructions

    23
  • Relative Offset

    23
    • Table 12. Boolean Instructions

      23
  • Jump Instructions

    24
    • Table 13. Unconditional Jump Instructions

      24
  • Machine Cycles

    25
    • Table 14. Conditional Jump Instructions

      25
    • Figure 14. State Sequence in uPSD321x Devices

      26
• uPSD3200 HARDWARE DESCRIPTION

  27
  • Figure 15. uPSD321x Devices Functional Modules

    27
• MCU MODULE DISCRIPTION

  28
  • Special Function Registers

    28
    • Table 15. SFR Memory Map

      28
    • Table 16. List of all SFR

      29
    • Table 17. PSD Module Register Address Offset

      32
• INTERRUPT SYSTEM

  34
  • External Int0

    34
  • Timer 0 and 1 Interrupts

    34
  • Timer 2 Interrupt

    34
  • I2C Interrupt

    34
  • External Int1

    34
  • USB Interrupt

    34
    • Figure 16. Interrupt System

      35
  • USART Interrupt

    36
  • Interrupt Priority Structure

    36
  • Interrupts Enable Structure

    36
    • Table 18. Priority Levels

      36
    • Table 19. SFR Register

      36
    • Table 20. Description of the IE Bits.

      37
    • Table 21. Description of the IEA Bits

      37
    • Table 22. Description of the IP Bits

      37
    • Table 23. Description of the IPA Bits

      38
  • How Interrupts are Handled

    38
    • Table 24. Vector Addresses

      38
• POWER-SAVING MODE

  39
  • Idle Mode

    39
  • Power-Down Mode

    39
  • Power Control Register

    39
  • Idle Mode

    39
  • Power-Down Mode

    39
    • Table 25. Power-Saving Mode Power Consumption

      39
    • Table 26. Pin Status During Idle and Power-down Mode

      39
    • Table 27. Description of the PCON Bits

      40
• I/O PORTS (MCU Module)

  40
  • Table 28. I/O Port Functions

    40
  • Table 29. P1SFS (91H)

    41
  • Table 30. P3SFS (93H)

    41
  • Table 31. P4SFS (94H)

    41
  • PORT Type and Description

    42
    • Figure 17. PORT Type and Description (Part 1)

      42
    • Figure 18. PORT Type and Description (Part 2)

      43
• OSCILLATOR

  44
  • Figure 19. Oscillator

    44
• SUPERVISORY

  45
  • External Reset

    45
  • Low VDD Voltage Reset

    45
  • Watchdog Timer Overflow

    45
  • USB Reset

    45
    • Figure 20. RESET Configuration

      45
• WATCHDOG TIMER

  46
  • Table 32. Watchdog Timer Key Register (WDKEY: 0AEH)

    46
  • Table 33. Description of the WDKEY Bits

    46
  • Figure 21. RESET Pulse Width

    47
  • Table 34. Watchdog Timer Clear Register (WDRST: 0A6H)

    47
  • Table 35. Description of the WDRST Bits

    47
• TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2)

  48
  • Timer 0 and Timer 1

    48
    • Table 36. Control Register (TCON)

      48
    • Table 37. Description of the TCON Bits

      48
    • Table 38. TMOD Register (TMOD)

      48
    • Table 39. Description of the TMOD Bits

      49
    • Figure 22. Timer/Counter Mode 0: 13-bit Counter

      50
  • Timer 2

    51
    • Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload

      51
    • Table 40. Timer/Counter 2 Control Register (T2CON)

      51
    • Table 41. Timer/Counter 2 Operating Modes

      52
    • Table 42. Description of the T2CON Bits

      52
    • Figure 24. Timer 2 in Capture Mode

      53
    • Figure 25. Timer 2 in Auto-Reload Mode

      53
    • Figure 26. Timer/Counter Mode 3: Two 8-bit Counters

      54
• STANDARD SERIAL INTERFACE (UART)

  55
  • Multiprocessor Communications

    55
  • Serial Port Control Register

    56
    • Figure 27. Serial Port Mode 0, Block Diagram

      56
    • Table 43. Serial Port Control Register (SCON)

      56
    • Table 44. Description of the SCON Bits

      57
    • Table 45. Timer 1-Generated Commonly Used Baud Rates

      59
    • Figure 28. Serial Port Mode 0, Waveforms

      60
    • Figure 29. Serial Port Mode 1, Block Diagram

      61
    • Figure 30. Serial Port Mode 1, Waveforms

      61
    • Figure 31. Serial Port Mode 2, Block Diagram

      63
    • Figure 32. Serial Port Mode 2, Waveforms

      63
    • Figure 33. Serial Port Mode 3, Block Diagram

      64
    • Figure 34. Serial Port Mode 3, Waveforms

      64
• ANALOG-TO-DIGITAL CONVERTOR (ADC)

  65
  • ADC Interrupt

    65
    • Figure 35. A/D Block Diagram

      65
    • Table 46. ADC SFR Memory Map

      66
    • Table 47. Description of the ACON Bits

      66
    • Table 48. ADC Clock Input

      66
• PULSE WIDTH MODULATION (PWM)

  67
  • 4-channel PWM Unit (PWM 0-3)

    67
    • Figure 36. Four-Channel 8-bit PWM Block Diagram

      68
    • Table 49. PWM SFR Memory Map

      69
  • Programmable Period 8-bit PWM

    70
    • Figure 37. Programmable PWM 4 Channel Block Diagram

      70
  • PWM 4 Channel Operation

    71
    • Figure 38. PWM 4 With Programmable Pulse Width and Frequency

      71
• I2C INTERFACE

  72
  • Figure 39. Block Diagram of the I2C Bus Serial I/O

    72
  • Table 50. Serial Control Register (S2CON)

    72
  • Table 51. Description of the S2CON Bits

    73
  • Table 52. Selection of the Serial Clock Frequency SCL in Master Mode

    73
  • Serial Status Register (S2STA)

    74
  • Data Shift Register (S2DAT)

    74
    • Table 53. Serial Status Register (S2STA)

      74
    • Table 54. Description of the S2STA Bits

      74
    • Table 55. Data Shift Register (S2DAT)

      74
  • Address Register (S2ADR)

    75
    • Table 56. Address Register (S2ADR)

      75
    • Table 57. Start /Stop Hold Time Detection Register (S2SETUP)

      75
    • Table 58. System Cock of 40MHz

      75
    • Table 59. System Clock Setup Examples

      75
• USB HARDWARE

  76
  • USB related registers

    76
    • Table 60. USB Address Register (UADR: 0EEh)

      76
    • Table 61. Description of the UADR Bits

      76
    • Table 62. USB Interrupt Enable Register (UIEN: 0E9h)

      77
    • Table 63. Description of the UIEN Bits

      77
    • Table 64. USB Interrupt Status Register (UISTA: 0E8h)

      78
    • Table 65. Description of the UISTA Bits

      78
    • Table 66. USB Endpoint0 Transmit Control Register (UCON0: 0EAh)

      79
    • Table 67. Description of the UCON0 Bits

      79
    • Table 68. USB Endpoint1 (and 2) Transmit Control Register (UCON1: 0EBh)

      80
    • Table 69. Description of the UCON1 Bits

      80
    • Table 70. USB Control Register (UCON2: 0ECh)

      81
    • Table 71. Description of the UCON2 Bits

      81
    • Table 72. USB Endpoint0 Status Register (USTA: 0EDh)

      81
    • Table 73. Description of the USTA Bits

      81
    • Table 74. USB Endpoint0 Data Receive Register (UDR0: 0EFh)

      81
    • Table 75. USB Endpoint0 Data Transmit Register (UDT0: 0E7h)

      81
    • Table 76. USB Endpoint1 Data Transmit Register (UDT1: 0E6h)

      81
    • Table 77. USB SFR Memory Map

      82
  • Transceiver

    83
    • Figure 40. Low Speed Driver Signal Waveforms

      83
    • Table 78. Transceiver DC Characteristics

      84
    • Table 79. Transceiver AC Characteristics

      84
  • Receiver Characteristics

    85
    • Figure 41. Differential Input Sensitivity Over Entire Common Mode Range

      85
  • External USB Pull-Up Resistor

    86
    • Figure 42. USB Data Signal Timing and Voltage Levels

      86
    • Figure 43. Receiver Jitter Tolerance

      86
    • Figure 44. Differential to EOP Transition Skew and EOP Width

      87
    • Figure 45. Differential Data Jitter

      87
• PSD MODULE

  88
  • Functional Overview

    88
    • Figure 46. PSD MODULE Block Diagram

      89
  • In-System Programming (ISP)

    90
    • Table 80. Methods of Programming Different Functional Blocks of the PSD MODULE

      90
• DEVELOPMENT SYSTEM

  91
  • Figure 47. PSDsoft Express Development Tool

    91
• PSD MODULE REGISTER DESCRIPTION AND ADDRESS OFFSET

  92
  • Table 81. Register Address Offset

    92
• PSD MODULE DETAILED OPERATION

  93
• MEMORY BLOCKS

  93
  • Primary Flash Memory and Secondary Flash memory Description

    93
  • Memory Block Select Signals

    93
  • Instructions

    94
    • Table 82. Instructions

      95
  • Power-down Instruction and Power-up Mode

    96
  • READ

    96
    • Table 83. Status Bit

      97
  • Programming Flash Memory

    98
    • Figure 48. Data Polling Flowchart

      98
    • Figure 49. Data Toggle Flowchart

      99
  • Erasing Flash Memory

    100
  • Specific Features

    101
    • Table 84. Sector Protection/Security Bit Definition – Flash Protection Register

      101
    • Table 85. Sector Protection/Security Bit Definition – Secondary Flash Protection Register

      101
  • SRAM

    102
  • Sector Select and SRAM Select

    102
    • Figure 50. Priority Level of Memory and I/O Components in the PSD MODULE

      102
    • Table 86. VM Register

      103
    • Figure 51. Separate Space Mode

      104
    • Figure 52. Combined Space Mode

      104
  • Page Register

    105
    • Figure 53. Page Register

      105
• PLDs

  106
  • Table 87. DPLD and CPLD Inputs

    106
  • The Turbo Bit in PSD MODULE

    106
    • Figure 54. PLD Diagram

      107
  • Decode PLD (DPLD)

    108
    • Figure 55. DPLD Logic Array

      108
  • Complex PLD (CPLD)

    109
    • Figure 56. Macrocell and I/O Port

      109
  • Output Macrocell (OMC)

    110
    • Table 88. Output Macrocell Port and Data Bit Assignments

      110
  • Product Term Allocator

    111
    • Figure 57. CPLD Output Macrocell

      111
  • Input Macrocells (IMC)

    112
    • Figure 58. Input Macrocell

      112
• I/O PORTS (PSD MODULE)

  113
  • General Port Architecture

    113
    • Figure 59. General I/O Port Architecture

      113
  • Port Operating Modes

    114
  • MCU I/O Mode

    114
  • PLD I/O Mode

    114
  • Address Out Mode

    114
  • Peripheral I/O Mode

    114
  • JTAG In-System Programming (ISP)

    114
    • Figure 60. Peripheral I/O Mode

      115
    • Table 89. Port Operating Modes

      115
    • Table 90. Port Operating Mode Settings

      115
    • Table 91. I/O Port Latched Address Output Assignments

      115
  • Port Configuration Registers (PCR)

    116
    • Table 92. Port Configuration Registers (PCR)

      116
    • Table 93. Port Pin Direction Control, Output Enable P.T. Not Defined

      116
    • Table 94. Port Pin Direction Control, Output Enable P.T. Defined

      116
    • Table 95. Port Direction Assignment Example

      116
  • Port Data Registers

    117
    • Table 96. Drive Register Pin Assignment

      117
    • Table 97. Port Data Registers

      117
  • Ports A and B – Functionality and Structure

    118
    • Figure 61. Port A and Port B Structure

      118
  • Port C – Functionality and Structure

    119
    • Figure 62. Port C Structure

      119
  • Port D – Functionality and Structure

    120
    • Figure 63. Port D Structure

      120
  • External Chip Select

    121
    • Figure 64. Port D External Chip Select Signals

      121
• POWER MANAGEMENT

  122
  • Figure 65. APD Unit

    122
  • Figure 66. Enable Power-down Flow Chart

    123
  • Table 98. Power-down Mode’s Effect on Ports

    123
  • PLD Power Management

    124
  • PSD Chip Select Input (CSI, PD2)

    124
  • Input Clock

    124
  • Input Control Signals

    124
    • Table 99. Power Management Mode Registers PMMR0

      124
    • Table 100. Power Management Mode Registers PMMR2

      125
    • Table 101. APD Counter Operation

      125
• RESET TIMING AND DEVICE STATUS AT RESET

  126
  • Warm RESET

    126
  • I/O Pin, Register and PLD Status at RESET

    126
    • Figure 67. Reset (RESET) Timing

      126
    • Table 102. Status During Power-on RESET, Warm RESET and Power-down Mode

      126
• PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE

  127
  • Standard JTAG Signals

    127
    • Table 103. JTAG Port Signals

      127
  • JTAG Extensions

    127
  • Security and Flash memory Protection

    127
• INITIAL DELIVERY STATE

  127
• AC/DC PARAMETERS

  128
  • Figure 68. PLD ICC /Frequency Consumption (5V range)

    128
  • Figure 69. PLD ICC /Frequency Consumption (3V range)

    128
  • Table 104. PSD MODULE Example, Typ. Power Calculation at VCC = 5.0V (Turbo Mode Off)

    129
• MAXIMUM RATING

  130
  • Table 105. Absolute Maximum Ratings

    130
• EMC CHARACTERISTICS

  131
  • Functional EMS (Electromagnetic Susceptibility)

    131
  • Designing Hardened Software To Avoid Noise Problems

    131
  • Absolute Maximum Ratings (Electrical Sensitivity)

    131
    • Table 106. EMS Test Results

      131
    • Table 107. ESD Absolute Maximum Ratings

      131
    • Table 108. Latch-up and Dynamic Latch-up Electrical Sensitivities

      132
• DC AND AC PARAMETERS

  133
  • Table 109. Operating Conditions (5V Devices)

    133
  • Table 110. Operating Conditions (3V Devices)

    133
  • Table 111. AC Signal Letter Symbols for Timing

    133
  • Table 112. AC Signal Behavior Symbols for Timing

    133
  • Figure 70. Switching Waveforms – Key

    134
  • Table 113. Major Parameters

    135
  • Table 114. DC Characteristics (5V Devices)

    136
  • Table 115. DC Characteristics (3V Devices)

    138
  • Figure 71. External Program Memory READ Cycle

    140
  • Table 116. External Program Memory AC Characteristics (with the 5V MCU Module)

    140
  • Table 117. External Program Memory AC Characteristics (with the 3V MCU Module)

    141
  • Figure 72. External Data Memory READ Cycle

    142
  • Table 118. External Clock Drive (with the 5V MCU Module)

    142
  • Table 119. External Clock Drive (with the 3V MCU Module)

    142
  • Figure 73. External Data Memory WRITE Cycle

    143
  • Table 120. External Data Memory AC Characteristics (with the 5V MCU Module)

    143
  • Table 121. External Data Memory AC Characteristics (with the 3V MCU Module)

    144
  • Table 122. A/D Analog Specification

    144
  • Figure 74. Input to Output Disable / Enable

    145
  • Table 123. CPLD Combinatorial Timing (5V Devices)

    145
  • Table 124. CPLD Combinatorial Timing (3V Devices)

    145
  • Figure 75. Synchronous Clock Mode Timing – PLD

    146
  • Table 125. CPLD Macrocell Synchronous Clock Mode Timing (5V Devices)

    146
  • Table 126. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices)

    147
  • Figure 76. Asynchronous RESET / Preset

    147
  • Figure 77. Asynchronous Clock Mode Timing (Product Term Clock)

    147
  • Table 127. CPLD Macrocell Asynchronous Clock Mode Timing (5V Devices)

    148
  • Table 128. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices)

    148
  • Figure 78. Input Macrocell Timing (Product Term Clock)

    149
  • Table 129. Input Macrocell Timing (5V Devices)

    149
  • Table 130. Input Macrocell Timing (3V Devices)

    149
  • Table 131. Program, WRITE and Erase Times (5V Devices)

    150
  • Table 132. Program, WRITE and Erase Times (3V Devices)

    150
  • Figure 79. Peripheral I/O READ Timing

    151
  • Table 133. Port A Peripheral Data Mode READ Timing (5V Devices)

    151
  • Table 134. Port A Peripheral Data Mode READ Timing (3V Devices)

    151
  • Figure 80. Peripheral I/O WRITE Timing

    152
  • Table 135. Port A Peripheral Data Mode WRITE Timing (5V Devices)

    152
  • Table 136. Port A Peripheral Data Mode WRITE Timing (3V Devices)

    152
  • Figure 81. Reset (RESET) Timing

    153
  • Table 137. Reset (RESET) Timing (5V Devices)

    153
  • Table 138. Reset (RESET) Timing (3V Devices)

    153
  • Table 139. VSTBYON Definitions Timing (5V Devices)

    153
  • Table 140. VSTBYON Timing (3V Devices)

    153
  • Figure 82. ISC Timing

    154
  • Table 141. ISC Timing (5V Devices)

    154
  • Table 142. ISC Timing (3V Devices)

    155
  • Figure 83. MCU Module AC Measurement I/O Waveform

    155
  • Figure 84. PSD MODULE AC Float I/O Waveform

    155
  • Figure 85. External Clock Cycle

    156
  • Figure 86. Recommended Oscillator Circuits

    156
  • Figure 87. PSD MODULE AC Measurement I/O Waveform

    156
  • Figure 88. PSD MODULEAC Measurement Load Circuit

    156
  • Table 143. Capacitance

    156
• PACKAGE MECHANICAL INFORMATION

  157
  • Figure 89. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Outline

    157
  • Table 144. TQFP52 – 52-lead Plastic Thin, Quad, Flat Package Mechanical Data

    158
  • Figure 90. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Outline

    159
  • Table 145. TQFP80 – 80-lead Plastic Thin, Quad, Flat Package Mechanical Data

    160
• PART NUMBERING

  161
  • Table 146. Ordering Information Scheme

    161
• REVISION HISTORY

  162
  • Table 147. Document Revision History

    162